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| dual, 16-bit, 1600 msps, txdac+ digital-to-analog converter data sheet ad9142a rev. a document feedbac k information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2013C2014 analog devices, inc. all rights reserved. technical support www.analog.com features supports input data rate up to 575 mhz very small inherent latency variation: <2 dac clock cycles proprietary low spurious and distortion design 6-carrier gsm aclr = 79 dbc at 200 mhz if sfdr > 85 dbc (bandwidth = 300 mhz) at zif flexible 16-bit lvds interface supports word and byte load data interface dll sample error detection and parity multiple chip synchronization fixed latency and data generator latency compensation selectable 2, 4, 8 interpolation filter low power architecture f s /4 power saving coarse mixer input signal power detection emergency stop for downstream analog circuitry protection fifo error detection on-chip numeric control oscillator allows carrier placement anywhere in the dac nyquist bandwidth transmit enable function for extra power saving high performance, low noise pll clock multiplier digital gain and phase adjustment for sideband suppression digital inverse sinc filter low power: 1.8 w at 1.6 gsps, 1.5 w at 1.25 gsps, full operating conditions 72-lead lfcsp applications wireless communications: 3g/4g and mc-gsm base stations, wideband repeaters, software defined radios wideband communications: point-to-point, lmds/mmds transmit diversity/mimo instrumentation automated test equipment general description the ad9142a is a dual, 16-bit, high dynamic range digital-to- analog converter (dac) that provides a sample rate of 1600 msps, permitting a multicarrier generation up to the nyquist frequency. the ad9142a txdac+? includes features optimized for direct conversion transmit applications, including complex digital mod- ulation, input signal power detection, and gain, phase, and offset compensation. the dac outputs are optimized to interface seam- lessly with analog quadrature modulators, such as the adl537x f-mod series and the adrf670x series from analog devices, inc. a 3-wire serial port interface provides for the programming/ readback of many internal parameters. full-scale output current can be programmed over a range of 9 ma to 33 ma. the ad9142a is available in a 72-lead lfcsp. product highlights 1. wide signal bandwidth (bw) enables emerging wideband and multiband wireless applications. 2. advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. 3. very small inherent latency variation simplifies both software and hardware design in the system. it allows easy multichip synchronization for most applications. 4. new low power architecture improves power efficiency (mw/mhz/channel) by 30%. 5. input signal power and fifo error detection simplify designs for downstream analog circuitry protection. 6. programmable transmit enable function allows easy design balance between power consumption and wakeup time.
ad9142a* product page quick links last content update: 11/01/2016 comparable parts view a parametric search of comparable parts evaluation kits ? ad9142a evaluation board documentation application notes ? an-1342: ad9142 to ad9142a migration data sheet ? ad9142a: dual, 16-bit, 1600 msps, txdac+ digital-to- analog converter data sheet tools and simulations ? ad9142a ibis model reference designs ? cn0375 reference materials press ? analog devices introduces high-performance rf ics for multi-band base stations and microwave point-to-point radios design resources ? ad9142a material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad9142a engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. ad9142a data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general descript ion ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 4 functional block diagram .............................................................. 5 specifications ..................................................................................... 6 dc specificati ons ......................................................................... 6 digital specifications ................................................................... 8 dac latency specifications ........................................................ 9 latency variation specifications ................................................ 9 ac specifications ........................................................................ 10 operating speed specifications ................................................ 10 absolute maximum ratings ..................................................... 11 thermal resistance .................................................................... 11 esd caution ................................................................................ 11 pin configuration and function descr iptions ........................... 12 typical performance characteristics ........................................... 15 ter mi nolo g y .................................................................................... 20 serial port oper ation ..................................................................... 21 data format ................................................................................ 21 serial port pin descriptions ...................................................... 21 serial port options ..................................................................... 21 data interface .................................................................................. 23 lvds input data ports .............................................................. 23 word interface mode ................................................................. 23 byte interface mode ................................................................... 23 data int erface configuration options .................................... 23 dll interface mode ................................................................... 23 parity ............................................................................................ 26 sed operation ............................................................................ 26 sed example ............................................................................... 27 delay line interface mode ........................................................ 27 fifo operation .............................................................................. 29 resetting the fifo ..................................................................... 30 serial port initiated fifo reset ............................................... 30 f rame initiated fifo reset ....................................................... 30 digital datapath .............................................................................. 32 interpolation filters ................................................................... 32 digital modulation ..................................................................... 34 datapath configuration ............................................................ 35 digital quadrature gain and phase adjustment ................... 35 dc offset adjustment ............................................................... 35 inverse sinc filter ....................................................................... 36 input signal power detection and protection ........................ 36 transmit enable function ......................................................... 37 digital function configuration ............................................... 37 multidevice synchronization and fixed latency ....................... 38 very small inherent latency variation ................................... 38 further reducing the latency variation ................................. 38 synchronization implementation ............................................ 39 synchronization procedures ..................................................... 39 interrupt request operation ........................................................ 40 interrupt working mechanism ................................................ 40 interrupt service routine .......................................................... 40 te mperature sensor ....................................................................... 41 dac input clock configurations ................................................ 42 driving the dacclk and refclk inputs ........................... 42 direct clocking .......................................................................... 42 clock multip lication .................................................................. 42 pll settings ................................................................................ 43 configuring the vco tuning band ........................................ 43 automatic vco band select .................................................... 43 manual vco band select ......................................................... 43 pll enable s equence ................................................................. 43 analog outputs ............................................................................... 44 transmit dac operation .......................................................... 44 interfacing to modulators ......................................................... 45 reducing lo leakage and unwanted sidebands .................. 46 example start - up routine ............................................................ 47 device configuration and start - up sequence 1 .................... 47 device configuration and start - up sequence 2 .................... 47 device configuration register map and description ............... 49 spi configure register .............................................................. 52 power - down control register ................................................. 52 interrupt enable0 register ........................................................ 52 interrupt enable1 register ........................................................ 53 interrupt flag0 register ............................................................. 53 interrupt flag1 register ............................................................. 53 inte rrupt select0 register .......................................................... 54 rev. a | page 2 of 72 data sheet ad9142a interrupt select1 register ........................................................... 54 frame mode register .................................................................. 54 data control 0 register .............................................................. 55 data control 1 register .............................................................. 55 data control 2 register .............................................................. 55 data control 3 register .............................................................. 55 data status 0 register ................................................................. 55 dac cl ock receiver control register ..................................... 56 ref clock receiver control register ........................................ 56 pll control 0 register ............................................................... 56 pll control 2 register ............................................................... 57 pll co ntrol 3 register ............................................................... 57 pll status 0 register .................................................................. 57 pll status 1 register .................................................................. 58 idac fs adjust lsb register .................................................... 58 idac fs adjust msb register .................................................. 58 qdac fs adjust lsb register .................................................. 58 qdac fs adjust msb register ................................................ 58 die temperature sensor control register ............................... 59 die temperature lsb register .................................................. 59 die temperature msb register ................................................. 59 chip id register .......................................................................... 59 interrupt configuation register ............................................... 59 sync control register ................................................................. 60 frame reset control register .................................................... 60 fifo level configuration register .......................................... 60 fifo level readback register .................................................. 61 fifo control register ................................................................ 61 data format select register ....................................................... 61 datapath control register ......................................................... 61 interpolation control register .................................................. 62 over threshold control 0 register .......................................... 62 over threshold control 1 register .......................................... 62 over threshold control 2 register .......................................... 62 input power readback lsb register ........................................ 62 input power readback msb register ....................................... 63 nco control register ................................................................ 63 nco frequency tuning word 0 register ............................... 63 nco frequency tuning word 1 register ............................... 63 nco frequency tuning word 2 register ............................... 63 nco frequency tuning word 3 register ............................... 64 nco phase offset 0 register .................................................... 64 nco phase offset 1 register .................................................... 64 iq phase adjust 0 register ........................................................ 64 iq phase adjust 1 register ........................................................ 64 power down data input 0 register .......................................... 65 idac dc offset 0 register ....................................................... 65 id ac dc offset 1 register ....................................................... 65 qdac dc offset 0 register ...................................................... 65 qdac dc offset 1 register ...................................................... 65 idac gain adjust register ....................................................... 65 qd ac gain adjust register ...................................................... 66 gain step control 0 register ..................................................... 66 gain step control 1 register ..................................................... 66 tx enable control register ....................................................... 66 da c output control register .................................................. 67 dll cell enable 0 register ........................................................ 67 dll cell enable 1 register ........................................................ 67 sed control register ................................................................. 67 sed patt ern i0 low bits register .............................................. 68 sed pattern i0 high bits register ............................................ 68 sed pattern q0 low bits register ............................................ 68 sed pattern q0 high bits register .......................................... 68 sed pattern i1 low bits register .............................................. 68 sed pattern i1 high bits register ............................................ 68 sed pattern q1 low bits register ............................................ 68 sed pattern q1 high bits register .......................................... 69 parity control register ............................................................... 69 parity error rising edge register ............................................. 69 parity error falling edge register ............................................ 69 version register .......................................................................... 69 dac latency and system skews ................................................... 70 dac latency variations ............................................................. 70 fifo latency variation .............................................................. 70 clock generation latency variation ........................................ 71 correcting system skews ........................................................... 71 packaging and ordering information .......................................... 72 outline dimensions ................................................................... 72 ordering guide ........................................................................... 72 rev. a | page 3 of 72 ad9142a data sheet rev. a | page 4 of 72 revision history 5/14rev. 0 to rev. a change to table 25 ......................................................................... 51 changes to table 103 ...................................................................... 69 12/13revision 0: initial version data sheet ad9142a rev. a | page 5 of 72 functional block diagram figure 1. ref and bias fsadj vref power-on reset multichip synchronization serial input/output port programming registers sdio sclk cs reset txen irq1 irq2 dacclkp dacclkn refp/syncp refn/syncn clock multiplier clk rcvr ref rcvr dac_clk lvds data receiver input power detection dll 13-tap fifo 8-sample d15p/d15n d0p/d0n dcip/dcin interface ctrl fifo ctrl sed ctrl interp mode ctrl1 hb1 2 interp mode ctrl2 hb2 2 interp mode ctrl3 hb3 2 dac_clk inv sinc gain and phase control dc offset control overthreshold protection complex modulation f dac /4 mod nco dac 1 16-bit iout1p iout1n 16 dac 2 16-bit iout2p iout2n 16 10 gain 1 10 gain 2 internal clock timing and control logic dac clk sync ad9142a framep/parityp framen/parityn sed 11901-001 ad9142a data sheet specifications dc specifications t min to t max , avdd33 = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i outfs = 20 ma, maximum sample rate, unless otherwise noted. table 1. parameter test conditions/comments min typ max unit resolution 16 bits accuracy differential nonlinearity (dnl) 2.1 lsb integral nonlinearity (inl) 3.7 lsb main dac outputs offset error ? 0.001 0 + 0.001 % fsr gain error w ith internal reference ? 3.2 + 2 + 4.7 % fsr full - scale output current based on a 10 k external resistor between fsadj and avss 19.06 19.8 20.6 ma output compliance range 1.0 +1.0 v output resistance 10 m ? gain dac monotonicity guaranteed settling time to within 0.5 lsb 20 ns main dac temperature drift offset 0.04 ppm/ c gain 100 ppm/ c reference voltage 30 ppm/ c reference internal reference voltage 1.17 1.19 v output resistance 5 k ? analog supply voltages avdd33 3.13 3.3 3.47 v cvdd18 1.7 1.8 1.9 v digital supply voltages dvdd18 1.7 1.8 1.9 v dvdd18 variation over operating conditions 1 2.5% +2.5% v power consumption 2 mode f dac = 737.28 msps nco off 925 mw nco on 1217 mw 2 mode f dac = 983.04 msps nco off 1135 mw nco on 1520 mw 4 mode f dac = 737.28 msps nco off 852 mw nco on 1144 mw 4 mode f dac = 983.04 msps nco off 1040 mw nco on 1425 mw 4 mode f dac = 1228.8 msps nco off 1230 mw nco on 1725 mw 4 mode f dac = 1474.56 msps nco off 1405 mw nco on 1990 mw rev. a | page 6 of 72 data sheet ad9142a parameter test conditions/comments min typ max unit 8 mode f dac = 1600 msps nco off 1350 mw nco on 1984 mw phase - lock loop (pll) 70 mw inverse sinc f dac = 1474.56 msps 113 mw reduced power mode (power - down) 96.6 mw avdd33 1.5 ma cvdd18 42.3 ma dvdd18 8.6 ma operating range ? 40 +25 +85 c 1 this term specifies the maximum allowable variation of dvdd18 over operating conditions compared with the dvdd18 presented to the device at the time the data interface dll is enabled. rev. a | page 7 of 72 ad9142a data sheet digital specifications t min to t max , avdd33 = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i outfs = 20 ma, maximum sampl e rate, unless otherwise noted. table 2. parameter symbol test conditions /comments min typ max unit cmos input logic level input logic high d vdd 18 = 1.8 v 1.2 v logic low d vdd 18 = 1.8 v 0.6 v cmos output logic level output logic high d vdd 18 = 1.8 v 1.4 v logic low d vdd 18 = 1.8 v 0.4 v lvds receiver inputs data, frame signal, and dci inputs input voltage range v ia or v ib 825 1675 mv input differential threshold v idth ? 175 +1 75 mv input differential hysteresis v idthh to v idthl 20 mv receiver differential input impedance r in 100 dll speed range 250 575 mhz dac update rate 1600 msps dac adjusted update rate 2 interpolation 575 msps dac clock input (dacclkp, dacclkn) differential peak -to - peak voltage 100 500 2000 mv common - mode voltage self biased input, ac - couple d 1.25 v refclk/syncclk input (refp/syncp, refn/syncn) differential peak -to - peak voltage 100 500 2000 mv common - mode voltage 1.25 v input clock frequency 1 .03 ghz f vco 2. 07 g hz 450 mhz serial p ort interface maximum clock rate sclk 40 mhz minimum pulse width high t pwh 12.5 ns low t pw l 12.5 ns sdi o to sclk setup time t ds 1.5 ns sdi o to sclk hold time t dh 0.68 ns cs to sclk setup time t dcsb 2.38 1.4 ns cs to sclk hold time t dcsb 9.6 ns sdio to sclk delay t dv wait time for valid output from sdio 11 ns sdi o high -z to cs time for sdio to relinquish the output bus 8.5 ns sdio logic level voltage in put high v ih 1.2 1.8 v voltage in put low v il 0 0.5 v voltage out put high i ih with 2 ma loading 1.36 2 v voltage out put low i il with 2 ma loading 0 0.45 v rev. a | page 8 of 72 data sheet ad9142a dac latency specifications t min to t max , avdd33 = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i outfs = 20 ma, fifo l evel is set to 4 (half of the fifo depth), unless otherwise noted. table 3. parameter test conditions/comments min typ max unit word interface mode fine/coarse modulation, inverse sinc, gain/phase compensation off 2 interpolation 134 dacclk c ycles 4 interpolation 244 dacclk c ycles 8 interpolation 481 dacclk c ycles byte interface mode fine/coarse modulation, inverse sinc, gain/phase compensation off 2 interpolation 145 dacclk c ycles 4 interpolation 271 dacclk c ycles 8 interpolation 506 dacclk c ycles individual function blocks modulation fine 17 dacclk c ycles coarse 10 dacclk c ycles inverse sinc 20 dacclk c ycles phase compensation 12 dacclk c ycles gain compensation 16 dacclk c y cles latency v ariation specifications table 4. parameter min typ max unit dac latency variation 1 sync o ff 1 2 dacclk cycles sync o n 0 1 dacclk cycles 1 dac latency is defined as the elapsed time from a data sample clocked at the input to the ad9142a until the analog output begins to change. rev. a | page 9 of 72 ad9142a data sheet ac specifications t min to t max , avdd33 = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i outfs = 20 ma, maximum sample rate, unless otherwise noted. table 5. parameter test conditions/comments min typ max unit spurious - free dynamic range (sfdr) ? 14 dbfs single tone f dac = 737.28 msps f out = 200 mhz bw = 125 mhz 85 dbc bw = 270 mhz 80 dbc f dac = 983.04 msps f out = 200 mhz bw = 360 mhz 85 dbc f dac = 1228.8 msps f out = 280 mhz bw = 200 mhz 85 dbc bw = 500 mhz 75 dbc f dac = 1474.56 msps bw = 737 mhz f out = 10 mhz 85 dbc bw = 400 mhz f out = 280 mhz 80 dbc two - tone intermodulation distortion (imd) ? 12 dbfs each tone f dac = 737.28 msps f out = 200 mhz 80 dbc f dac = 983.04 msps f out = 200 mhz 82 dbc f dac = 1228.8 msps f out = 280 mhz 80 dbc f dac = 1474.56 msps f out = 10 mhz 85 dbc f out = 280 mhz 79 dbc noise spectral density (nsd ) e ight - tone, 500 k h z tone spacing f dac = 737.28 msps f out = 200 mhz ? 160 dbm/hz f dac = 983.04 msps f out = 200 mhz ? 161.5 dbm/hz f dac = 1228.8 msps f out = 280 mhz ? 164.5 dbm/hz f dac = 1474.56 msps f out = 10 mhz ? 166 dbm/hz f out = 280 mhz ? 162.5 dbm/hz w - cdma adjacent channel leakage ratio (aclr) single c arrier f dac = 983.04 msps f out = 200 mhz 81 dbc f dac = 1228.8 msps f out = 20 mhz 83 dbc f out = 280 mhz 80 dbc f dac = 1474.56 msps f out = 20 mhz 81 dbc f out = 280 mhz 80 dbc w - cdma second ( aclr ) single carrier f dac = 983.04 msps f out = 200 mhz 85 dbc f dac = 1228.8 msps f out = 20 mhz 86 dbc f out = 280 mhz 8 6 dbc f dac = 1474.56 msps f out = 20 mhz 86 dbc f out = 280 mhz 85 dbc operating speed specifications t able 6. interpolation factor dvdd18, cvdd18 = 1.8 v 5% dvdd18, cvdd18 = 1. 9 v 5% or 1.8 v 2% dvdd18, cvdd18 = 1. 9 v 2% f dci (msps ) max imum f d ac (msp s) max imum f dci (msps ) max imum f d ac (msp s) max imum f dci (msps ) max imum f dac (msps ) max imum 2 575 1150 575 1150 575 1150 4 350 1400 375 1500 400 1600 8 175 1400 187.5 1500 200 1600 rev. a | page 10 of 72 data sheet ad9142a absolute maximum rat ings table 7. parameter rating avdd33 to gnd ? 0.3 v to +3.6 v dvdd18, cvdd18 to gnd ? 0.3 v to +2.1 v fsadj, vref, iout1p , iout1n, iout2p , iout2n to gnd ? 0.3 v to avdd33 + 0.3 v d15p to d0p , d15n to d0n, framep/parityp, framen/parityn , dcip , dcin to gn d ? 0.3 v to dvdd18 + 0.3 v dacclkp , dacclkn, refp , syncp , refn , syncn to gn d ? 0.3 v to cvdd18 + 0.3 v reset , irq1 , irq2 , cs , sclk, sdio to gn d ? 0.3 v to dvdd18 + 0.3 v junction temperature 125c storage temperature range ? 65c to +150c thermal resistance the exposed pad (epad) must be soldered to the ground plane (avss) for the 72 - lead lfcsp . the epad provides an electrical, thermal, and mechanical connection to the board. typical ja , jb , and jc values are specified for a 4 - layer board in still air. airflow increases heat dissipation, effectively reducing ja and jb . table 8 . thermal resistance package ja jb jc unit conditions 72- lead lfcsp 20.7 10.9 1.1 c/w epad soldered to ground plane esd caution s t r e s s es a b o ve t h o s e l i s t e d u n d e r a b s o l u t e m a x i m um r a t i n gs m a y c a u s e p e r m a n e n t dam a g e t o t h e d e v i c e . this is a s t r e s s r a t i n g o n l y ; fu n c t i o n a l o p e r a t i o n o f t h e d ev i c e a t t h e s e o r a n y o t h e r co n d i t i o ns a b o ve t h o s e indi c a t e d i n t h e o p e r a t i o na l s e c t i o n o f t h is s p e c i fi c a t ion is n o t i m p l i e d . e x p o su r e t o a b s o l u te ma x i m u m r a t in g c o n d i t i o n s fo r e x t e n d e d p e r i o d s m a y a ff e c t d e vi c e r e l i a b i l i t y . rev. a | page 11 of 72 ad9142a data sheet pin configuration an d function descripti ons figure 2 . pin configuration table 9 . pin function descriptions pin no. mnemonic description 1 c vdd18 1.8 v pll supply. cvdd18 supplies the clock receivers, clock multiplier, and clock distribution. 2 refp/syncp pll reference clock /synchronization clock input, positive. 3 refn/syncn pll reference clock /synchronization clock input, negative. 4 c vdd18 1.8 v pll supply. cvdd18 supplies the clock receivers, clock multiplier, and clock distribution. 5 reset reset, active low. cmos levels with respect to dvdd18. recommended reset pulse length is 1 s. 6 txen active high transmit path enable. cmos levels with res pect to dvdd18. a low level on this pin triggers three selectable actions in the dac. see table 87 for details. 7 dvdd18 1.8 v digital supply. pin 7 supplies power to the digital core, digital data ports, serial port input/output pins, reset , irq1 , and irq2 . 8 framep/parityp frame /parity input, positive. 9 framen/parityn frame /parity input, negative. 10 d15 p data bit 15 (msb), positive. 11 d15 n data bit 15 (msb), negative. 12 dvdd18 1.8 v digital supply. pin 12 supplies the power to the digital core and digital data ports, serial port input/output pins, reset , irq1 , and irq2 . 13 d14 p data bit 14 , positive. 14 d14 n data bit 14 , negative. 15 d13 p data bit 13 , positive. 16 d13 n data bit 13 , negative. 17 d12 p data bit 12 , positive. 18 d 12n data bit 12 , negative. 19 dvdd18 1.8 v digital supply. pin 19 s u pplies power to the digital core, digital data ports , serial port input/output pins , reset , irq 1 , and irq 2 . 20 d 11p data bit 11 , positive. 2 1 d 11 n data bit 11 , negative. 22 d 10p data bit 10 , positive. 23 d 10n data bit 10 , negative. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 cvdd18 refp/syncp refn/syncn cvdd18 reset txen dvdd18 framep/parityp framen/parityn d15p d15n dvdd18 d14p d14n d13p d13n 17 d12p 18 d12n 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 dvdd18 d11p d11n d10p d10n d9p d9n d8p d8n dcip dcin d7p d7n d6p d6n d5p 35 d5n 36 dvdd18 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 cs sclk sdio irq1 irq2 dvdd18 dvdd18 d0n d0p d1n d1p dvdd18 d2n d2p d3n d3p d4n d4p 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 cvdd18 cvdd18 vref fsadj avdd33 iout1p iout1n avdd33 cvdd18 cvdd18 dacclkp dacclkn cvdd18 cvdd18 avdd33 iout2n iout2p avdd33 ad9142a top view (not to scale) notes 1. exposed pad (epad) must be soldered to the ground plane (avss, dvss, cvss). the epad provides an electri - cal, thermal, and mechanical connection to the board. 1 1901-002 rev. a | page 12 of 72 data sheet ad9142a pin no. mnemonic description 24 d9 p data bit 9 , positive. 25 d9 n data bit 9 , negative. 26 d8 p data bit 8 , positive. 27 d8 n data bit 8 , negative. 2 8 dcip data clock input, positive. 29 dcin data clock input, negative. 30 d7 p data bit 7 , positive. 31 d7 n data bit 7 , negative. 32 d6 p data bit 6 , positive. 33 d6 n data bit 6 , negative. 3 4 d5 p data bit 5 , positive. 35 d5 n data bit 5 , negative. 36 dvdd18 1.8 v digital supply. pin 36 s u pplies power to the digital core, digital data ports , serial port input/output pins , reset , irq 1 , and irq 2 . 37 d4 p data bit 4 , positive. 38 d4 n data bit 4 , negative. 39 d3 p data bit 3 , positive. 40 d3 n data bit 3 , negative. 41 d2 p data bit 2 , positive. 42 d2 n data bit 2 , negative. 43 dvdd18 1.8 v digital supply. pin 43 s u pplies power to the digital core, digital data ports , serial port input/output pins , reset , irq 1 , and irq 2 . 44 d1 p data bit 1 , positive. 45 d1 n data bit 1 , negative. 46 d0 p data bit 0 , positive. 47 d0 n data bit 0 , negative. 48 dvdd18 1.8 v digital supply. pin 48 s u pplies power to the digital core, digital data ports , serial port input/output pins , reset , irq 1 , and irq 2 . 49 dvdd18 1.8 v digital supply. pin 49 supplies power to the digital core, digital data ports, serial port input/output pins, reset , irq 1 , and irq2 . 50 irq 2 second interrupt request. open - drain, active low output. connect an external pull - up to dvdd18 through a 10 k resistor. 51 irq 1 first interrupt request. open - drain, active low output. con nect an external pull - up to dvdd18 through a 10 k resistor. 52 sdio serial port data input/output. cmos levels with respect to dvdd18. 53 sclk serial port clock input . cmos l evels w ith r espect to dvdd18 . 54 cs serial port chip select . active l ow (cmos levels w ith respect to dvdd18 ). 55 avdd33 3.3 v analog supply. 5 6 iout2p qdac positive current output. 57 iout2n qdac negative current output. 58 avdd33 3.3 v analog supply. 59 cvdd18 1.8 v clock s upply. supplies clock receivers and clock distribution. 60 cvdd18 1.8 v clock s upply. supplies clock receivers and clock distribution. 61 dacclkn dac clock input, negative. 62 dacclkp dac clock input, posi tive. 63 cvdd18 1.8 v clock s upply. supplies clock receivers and clock distribution. 64 cvdd18 1.8 v clock s upply. supplies clock receivers and clock distribution. 65 avdd33 3.3 v analog supply. 66 iout1n i dac negative current output. 6 7 iout1p i dac positive current output. 68 avdd33 3.3 v analog supply. 69 fsadj full - scale current output adjust. place a 10 k resistor from this pin to gnd. 70 vref voltage reference. nominally 1.2 v output. decouple vref to gnd . rev. a | page 13 of 72 ad9142a data sheet pin no. mnemonic description 71 cvdd18 1.8 v clock s upply. pin 71 supplies the clock receivers, clock multiplier, and clock distri bution. 72 cvdd18 1.8 v clock s upply. pin 72 supplies the clock receivers, clock multiplier, and clock distribution. epad exposed pad. the exposed pad (epad) must be soldered to the ground plane (avss, dvss, cvss). t he epad provides an electrical, thermal, and mechanical connection to the board. rev. a | page 14 of 72 data sheet ad9142a typical performance characteristics figure 3 . single tone (0 dbfs) sfdr vs. f out in the first nyquist zone over f dac figure 4 . single tone second harmonic vs. f out in the first nyquist zone over digital bac k off , f dac = 1474.56 mhz figure 5 . single tone third harmonic vs. f out in the first nyquist zone over digital b ack off , f dac = 1474.56 mhz figure 6 . in- band , single tone sfd r ( e xcluding second h armonic) vs. f o ut in 80 mhz and 300 mhz b andwidths , f dac = 737.28 mhz figure 7 . in- band , single t one sfdr ( e xcluding second h armonic) vs. f out i n 80 mhz and 300 mhz bw, f dac = 983.04 mhz figure 8 . in- band , single tone sf dr ( e xcluding second h armonic) vs. f o ut in 80 mhz and 300 mhz b andwidths , f dac = 1228.8 mhz 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100 200 300 400 500 600 700 800 sfdr (dbc) f out (mhz) f dac = 737.28mhz f dac = 983.04mhz f dac = 1228.8mhz f dac = 1474.56mhz 1 1901-003 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100 200 300 400 500 600 700 800 second harmonic (dbc) f out (mhz) 0dbfs ?6dbfs ?12dbfs ?16dbfs 1 1901-005 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100 200 300 400 500 600 700 800 third harmonic (dbc) f out (mhz) 0dbfs ?6dbfs ?12dbfs ?16dbfs 1 1901-007 ?60 < ?85 ?85 ?80 ?75 ?70 ?65 0 20 40 60 80 100 140 180 120 160 200 in-band sfdr (dbc) f out (mhz) bw = 80mhz, ?6dbfs bw = 80mhz, ?12dbfs bw = 300mhz, ?6dbfs bw = 300mhz, ?12dbfs C85 means C85 1 1901-004 ?60 < ?85 ?85 ?80 ?75 ?70 ?65 0 300 250 200 150 100 50 in-band sfdr (dbc) f out (mhz) bw = 80mhz, ?6dbfs bw = 80mhz, ?12dbfs bw = 300mhz, ?6dbfs bw = 300mhz, ?12dbfs C85 means C85 1 1901-006 ?60 < ?85 ?85 ?80 ?75 ?70 ?65 0 350 300 250 200 150 100 50 in-band sfdr (dbc) f out (mhz) bw = 80mhz, ?6dbfs bw = 80mhz, ?12dbfs bw = 300mhz, ?6dbfs bw = 300mhz, ?12dbfs C85 means C85 1 1901-008 rev. a | page 15 of 72 ad9142a data sheet figure 9 . in- band , single to ne sfdr (e xcluding second h armonic) v s. f out in 80 mhz and 300 mhz b andwidths , f dac = 1474.56 mhz figure 10 . two tone , third imd vs. f out over f dac figure 11 . two tone , third i md vs. f out over digital back off , f dac = 1474.56 mhz figure 12 . two tone , third imd vs. f out over tone spacing , f dac = 1474.56 mhz figure 13 . single tone (0 dbfs) nsd vs. f out over f dac figure 14 . single tone nsd vs. f out over digital b ack off , f dac = 1474.56 mhz ?60 < ?85 ?85 ?80 ?75 ?70 ?65 0 350 300 250 200 150 100 50 in-band sfdr (dbc) f out (mhz) bw = 80mhz, ?6dbfs bw = 80mhz, ?12dbfs bw = 300mhz, ?6dbfs bw = 300mhz, ?12dbfs C85 means C85 1 1901-009 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100 200 300 400 500 600 700 800 imd (dbc) f out (mhz) f dac = 737.28mhz f dac = 983.04mhz f dac = 1228.8mhz f dac = 1474.56mhz 1 1901-0 1 1 0 ?120 ?100 ?80 ?60 ?40 ?20 0 800 600 700 500 400 300 200 100 imd (dbc) f out (mhz) 0dbfs ?6dbfs ?9dbfs 1 1901-013 0 ?120 ?100 ?80 ?60 ?40 ?20 0 800 600 700 500 400 300 200 100 imd (dbc) f out (mhz) 0.6mhz tone spacing 16mhz tone spacing 35mhz tone spacing 1 1901-010 ?152 ?168 ?166 ?164 ?162 ?160 ?158 ?156 ?154 0 100 200 300 400 500 600 700 800 nsd (dbm/hz) f out (mhz) f dac = 737.28mhz f dac = 983.04mhz f dac = 1228.8mhz f dac = 1474.56mhz 1 1901-012 ?152 ?168 ?166 ?164 ?162 ?160 ?158 ?156 ?154 0 100 200 300 400 500 600 700 800 nsd (dbm/hz) f out (mhz) 0dbfs ?6dbfs ?12dbfs ?16dbfs 1 1901-014 rev. a | page 16 of 72 data sheet ad9142a figure 15 . 1c wcdma nsd vs. f out , over f dac figure 16 . single tone nsd vs. f out , f dac = 1474.28 mhz, pll o n and o ff figure 17 . 1c wcdma, first a djacent aclr vs. f out , pll on and off figure 18 . 1c wcdma , second a djacent aclr vs. f out , pll on and off figure 19 . two tone , third imd p erformance, if = 280 mhz, f dac = 1474.28 mhz figure 20 . 1c wcdma aclr performance, if = 280 mhz, f dac = 1474.28 mhz ?150 ?152 ?170 ?168 ?166 ?164 ?162 ?160 ?158 ?156 ?154 0 100 200 300 400 500 600 700 800 nsd (dbm/hz) f out (mhz) 737.2mhz 983.04mhz 1228.8mhz 1474.56mhz 1 1901-200 ?150 ?152 ?168 ?166 ?164 ?162 ?160 ?158 ?156 ?154 0 100 200 300 400 500 600 700 800 nsd (dbm/hz) f out (mhz) pll off pll on 1 1901-015 ?60 ?85 ?80 ?75 ?70 ?65 0 100 200 300 400 500 600 700 800 aclr (dbc) f out (mhz) f dac = 1474.56mhz, pll off, 0dbfs f dac = 1474.56mhz, pll on, 0dbfs f dac = 1228.8mhz, pll off, 0dbfs f dac = 1228.8mhz, pll on, 0dbfs 1 1901-100 ?60 ?90 ?85 ?80 ?75 ?70 ?65 0 100 200 300 400 500 600 700 800 aclr (dbc) f out (mhz) f dac = 1474.56mhz, pll off, 0dbfs f dac = 1474.56mhz, pll on, 0dbfs f dac = 1228.8mhz, pll off, 0dbfs f dac = 1228.8mhz, pll on, 0dbfs 1 1901-101 1 1901-016 1 1901-017 rev. a | page 17 of 72 ad9142a data sheet figure 21 . single tone f da c = 1474.56 mhz, f out = 280 mhz, ? 14 dbfs figure 22 . 4 c wcdma aclr p erformance, if = 280 mhz, f dac = 1474.28 mhz figure 23 . sin gle tone sfdr f dac = 1474.56 mhz, 4 interpolation, f out = 10 mhz, ? 14 dbfs figure 24 . total power baseline consumption vs. f dac over interpolation figure 25 . dvdd18 supply current vs . f dac over interpolation figure 26 . dvdd18 supply current vs . f dac ove r digital functions 1 1901-018 1 1901-019 1 1901-020 1600 1400 400 600 800 1000 1200 200 1600 1400 1200 1000 800 600 400 total baseline power consumption (mw) f dac (mhz) 1 1901-021 2 4 8 600 500 200 400 100 300 0 200 400 600 800 1000 1200 1400 1600 dvdd supply current (ma) f dac (mhz) 1 1901-024 2 4 8 350 300 100 200 250 50 150 0 200 400 600 800 1000 1200 1400 1600 dvdd18 supply current (ma) f dac (mhz) 1 1901-022 nco inverse sinc digi t al gain and phase f s /4 modul a tion rev. a | page 18 of 72 data sheet ad9142a figure 27 . cvdd18, avdd33 supply current vs. f dac 250 200 150 100 50 200 400 600 800 1000 1200 1400 1600 supply current (ma) f dac (mhz) 1 1901-023 cvdd18, pll off avdd33 cvdd18, pll on rev. a | page 19 of 72 ad9142a data sheet terminology integral nonlinearity (inl) inl is the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. differential nonlinearity (dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. offset error offset error is t he deviation of the output current from the ideal of 0 ma . for iout1p, 0 ma output is expected when all inputs are set to 0. for iout1n, 0 ma output is expected when all inputs are set to 1. gain error gain error is t he difference between the actual and ideal output span. the actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. output compliance range the o utput c ompliance r ange is t he range of allowable voltage at the output of a current output dac. operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulti ng in nonlinear performance. temperature drift temperature drift is specified as the maximum change from the ambient (25c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full - scale range (fsr) per d egree celsius. for reference drift, the drift is reported in ppm per degree celsius. power supply rejection (psr) psr is t he maximum change in the full - scale output as the supplies are varied from minimum to maximum specified voltages. settling time settling t ime is t he time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. spurious - free dynamic range (sfdr) sfdr is t he difference, in decibels, between th e peak amplitude of the output signal and the peak spurious signal within the dc to nyquist frequency of the dac. typically, the interpol ation filters reject energy in this band . this specification, there fore, defines how well the interpolation filters wor k and the effect of other parasitic coupling paths on the dac output. signal -to - noise ratio (snr) snr is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency, excluding the fir st six harmonics and dc. the value for snr is expressed in decibels. interpolation filter if the digital inputs to the dac are sampled at a multiple rate of f data (interpolation rate), a digital filter can be constructed that has a sharp transition band ne ar f data /2. images that typically appear around f dac (output data rate) can be greatly suppressed. adjacent channel leakage ratio (aclr) aclr is the ratio in decibels relative to the carrier (dbc) between the measured power within a channel relative to its adjacent channel. complex imag e rejection in a traditional two - part upconversion, two images are created around the second if frequency. these images have the effect of wasting transmitter power and system bandwidth. by placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second if can be rejected. rev. a | page 20 of 72 data sheet ad9142a serial port operatio n the serial port is a flexible, synchronous serial communications port that allows easy interfacing to many industry standard micro - controllers and microprocessors. the serial i/o is compatible with most synchronous transfer formats, including both the moto rola ? spi and intel? ssr protocols. the interface allows read/write access to all registers that configure the ad9142a . msb - first or lsb - first transf er formats are supported. the serial port interface is a 3 - wire only interface. the input and output share a single pin input/output (sdio) . figure 28 . serial port interface pins there are two phases to a communication cycle with the ad9142a . phase 1 is the instruction cycle (the writing of an instruction byte into the device) , coincident with the first 16 sclk ri sing edges. the instruction word provides the serial port controller with information regarding the data transfer cycle, phase 2 , of the communication cyc le. the phase 1 instruction word defines whether the upcoming da ta transfer is a read or write , along with the sta rting register address for the next data transfer in the cycle . a logic high on the cs pin , followed by a logic low , resets the serial port timing to the initial state of the instruction cycle. from this state, the next 16 rising sclk edges represent the instruction bits of the current i/o operation. the remaining sclk edges are for phase 2 of the communication cycle. p hase 2 is the actual data transfer between the device and the system controller. phase 2 of the communication cycle is a transfer of one data byte . registers change immediately upon writing to the last bit of each transfer byte, except for the frequency tu ning word and nco phase offsets, which change only when the frequency tuning word (ftw) u pdate bit is set. data format the instruction byte contains the information shown in table 10 . table 10 . serial port i nstruction word i15 (msb) i[14:0] r/ w a[14:0] r/ w ( bit 15 of the instruction word ) determines whether a read or a write data transfer o ccurs after the instruction word write. log ic 1 indicates a read operation and logic 0 indicates a write operation. a14 to a0 ( bit 14 to bit 0 of the instruction word ) determine the register that is accessed during the data transfer portion of the com mun ication cycle. for multibyte transfers, a14 is the starting address ; t he device generates the remaining register addresses based on the spi_ lsb_first bit. serial port pin desc riptions serial clock (sclk) the serial clock pin synchronizes data to and from the device and runs the internal state machines. the maximum frequency of sclk is 40 mhz. all data input is registered on the rising edge of sclk. all data is driven out on the falling edge of sclk. chip s elect ( cs ) cs is a n active low input that starts and gates a communication cycle. it allows more than one device to be used on the same serial commu nications line . the sdio pins enter a high impedance state when th e cs input is high. during the communication cycle, cs should stay low. serial data i/o (sdio) th e sdio pin is a bidirectional data line. serial port options the serial p ort can support both msb - first and lsb - first data forma ts. this functionality is controlled by the spi_lsb_first bit ( register 0x00, bit 6). the default is msb first (lsb_first = 0). when spi_lsb_first = 0 (msb first), the instruction and data bits must be written from msb to lsb. multibyte data transfers in msb - first format start with an instruction word that includes the register address of the most significant data byte. subsequent data bytes must follow from high address to low address. in msb - first mode, the serial port internal word address generator dec rements for each data byte of the multibyte communication cycle. when spi_lsb_first = 1 (lsb first), the instruction and data bits must be written from lsb to msb. multibyte data transfers in lsb - first format start with an instruction word that includes th e register address of the least significant data byte. subsequent data bytes must follow from low address to high address. in lsb - f irst mode, the serial port internal word address generator increments for each da ta byte of the multibyte communication cycle . if the msb - first mode is active, the serial port controller data address decrements from the data address written toward 0x00 for multibyte i/o operations. if the lsb - first mode is active, the serial port controller data address increments from the data address written toward 0xff for m ultibyte i/o operations. 53 sclk 54 cs 52 sdio spi port 1 1901-025 rev. a | page 21 of 72 ad9142a data sheet figure 29 . serial register interface timing, msb first figure 30 . serial register interface timing, lsb first figure 31 . timing diagram for serial port register write figure 32 . timing diagram for serial port register read r/w a14 a13 a3 a2 a1 a0 d7 n d6 n d5 n d0 0 d1 0 d2 0 d3 0 instruction cycle data transfer cycle sclk sdio cs 1 1901-026 a0 a1 a2 a12 a13 a14 r/w d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n instruction cycle data transfer cycle sclk sdio cs 1 1901-027 sclk sdio cs instruction bit 14 instruction bit 15 t dcsb t ds t dh t pwh t pwl t sclk 1 1901-028 sclk sdio cs d at a bit n ? 1 d at a bit n t dv 1 1901-029 rev. a | page 22 of 72 data sheet ad9142a data interface lvds input data port s the ad9142a has a 16 - bit lvds bus that accepts 16 - bit i and q data either in word (16 - bit) or byte ( 8 - bit) formats. in the word interface mode, the data is sent over the entire 16 - bit data bus. in the byte interface mode, t he data is sent over the lower 8 - bit (d7 to d0) lvds bus. table 11 lists t he pin assignment of the bus and the spi register configuration for each mode . table 11. lvds input data modes interface mode pin assignment spi register config uration word d 15 to d0 register 0 x26 , b it 0 = 0 byte d7 to d 0 register 0 x26 , b it 0 = 1 word interface mode in word interface mode , the digital clock input ( dci ) signal is a reference bit that generate s a double data rate (ddr) data sampling clock. time align t he dci signal with the data. the i dac data follow s the rising edge of the dci, and the qdac data follow s the falling edge of the dci, as shown in figure 33 . figure 33 . timing diagram for word interface mode byte interface mode in byte interface mode, th e required sequence of the input data stream is i[15:8], i[7:0], q[15:8], q[7:0]. a frame sig nal is required to align the order of input data bytes properly . time align b oth t he dci signal and frame signal with the data. the rising edge of the frame indicates the start of the sequence. the frame can be either a one shot or periodical signal as long as its first rising edg e is correctly captured by the device. for a one shot frame , the frame pulse must be held at high for at least one dci cycle. for a periodical frame , the frequency needs to be f dci /(2 n) where n is a positive integer , that is, 1, 2, 3 , figure 34 is an example of signal timing in byte mode. figure 34 . timing diagram for byte interface mode data interface configuration options to provide more flexibility for the data interface , some additional options are listed in table 12. table 12. data interface configuration options register 0x26 description data_format (bit 7) select between b inary and two s c omplement format s. data_pairing (bit 6) indicate i/q data pairing on data input . this allows the i and q data that is received to be paired in various ways. data_bus_invert (bit 5) swap s the bit order of the data input port. remap s the input data from d [ 15:0] to d [0: 15 ] . dll interface mode a source synchronous lvds interface is used between the data host and ad9142a to achieve high data rates while simplifying the interface. the fpga or asic feeds the ad9142a with 16 - bit input data. along with the input data, the fpga or asic provides a ddr ( d ouble d ata r ate) data clock input (dci). a delay lock ed loop (dll) circuit designed to operate with dci clock rates between 250 and 5 75 mhz is used to generate a phase - shifted version of the dci, called dsc ( d ata s ampling c lock), to register the input data on both the rising and falling edges. as shown i n figure 35 , the dci clock edges must be coincident with the data bit transitions with minimum skew and jitter. the nominal sampling point of the input data occurs in the middle of the dci clock edges because this point corre sponds to the center of the data eye. this is also equivalent to a nominal phase shift of 90 of the dci clock. the data timing requirements are defined by a data v alid w indow (dvw) that is dependent on the data clock input skew, input data jitter, and the variations of the dll delay line across delay settings. the dvw is defined as dvw = t d ata p eriod ? t d ata skew C t data jitter the available margin for data interface timing is given by t m argin = dvw ? ( t s + t h ) the difference between the setup and hold times, which is also called the k eep o ut w indow, or kow, is the area where data transitions should not happen. the timing margin allows tuning of the dll delay setting by the user, see figure 36. from the figure, it can be seen that the ideal location for the dsc signal is 90 out of phase from the dci input. however, due to skew of the dci relative to the data, it may be necessary to change the dsc phase offset to sample the data at the center of its eye diagram. the sampling instance can be varied in discrete increments by of fsetting the nominal dll phase shift value of 90 via register 0x0a , bits[3:0]. this register is a signed value. the msb is the sign and the lsbs are the magnitude. the following equation defines the phase offset relationship: phase offset = 90 n 11.25, | n | < 7 where n is the dll phase offset setting. i 0 q 0 i 1 q 1 word inter f ace mode dci input data[15:0] 1 1901-030 i 0[15:8] i 0[7:0] q 0[15:8] q 0[7:0] byte inter f ace mode dci frame input data[7:0] 1 1901-031 rev. a | page 23 of 72 ad9142a data sheet figure 35 shows the dsc set up and hold times with respect to the dci signal and data sign als. figure 35 . lvds data port setup and hold times table 13 lists the values that are guaranteed over the operating conditions. these values were taken with a 50% duty cycle and a dci swing of 450 mv p - p. for best performance, the duty cycle variation should be kept below 5%, and the dci input should be as high as possible, up to 1200 mv p - p . table 13 . dll phase set up and hold times (guaranteed) frequency, f dci (mh) time (ps) data port set up and hold times (ps) at dll phase 3 0 3 307 t s ? 125 ? 385 ? 695 t h 834 1120 1417 368 t s ? 70 ? 305 ? 534 t h 753 967 1207 491 t s ? 81 ? 245 ? 402 t h 601 762 928 figure 36 . lvds d ata p ort t iming r equirements dci data dsc t s t h 1 1901-135 input data dci data eye t s data sample clock input data dci data sample clock data eye dll phase delay t data jitter t h t data jitter t h and t s t dci skew t data period t data period 1 1901-037 rev. a | page 24 of 72 data sheet ad9142a table 14. dll phase setup and hold times (typical) frequency, f dci 1 (mhz) time (ps) data port setup and hold times (ps) at dll phase ? 6 ? 5 ? 4 ? 3 ? 2 ? 1 0 +1 +2 +3 +4 +5 +6 250 t s ? 93 ? 196 ? 312 ? 416 ? 530 ? 658 ? 770 ? 878 ? 983 ? 1093 ? 1193 ? 1289 ? 1412 t h 468 579 707 825 947 1067 1188 1315 1442 1570 1697 1777 1876 275 t s ? 87 ? 172 ? 264 ? 364 ? 464 ? 556 ? 653 ? 756 ? 859 ? 956 ? 1053 ? 1151 ? 1251 t h 451 537 646 757 878 977 1092 1218 1311 1423 1537 1653 1728 300 t s ? 82 ? 166 ? 256 ? 341 ? 426 ? 515 ? 622 ? 715 ? 809 ? 900 ? 1001 ? 1097 ? 1184 t h 422 500 598 703 803 897 1000 1105 1203 1303 1411 1522 1612 325 t s ? 46 ? 114 ? 190 ? 271 ? 358 ? 447 ? 538 ? 612 ? 706 ? 806 ? 891 ? 966 ? 1044 t h 405 483 563 647 740 832 914 1000 1100 1200 1292 1380 1476 350 t s ? 23 ? 92 ? 180 ? 252 ? 328 ? 409 ? 491 ? 574 ? 654 ? 731 ? 819 ? 889 ? 959 t h 383 451 524 607 682 762 844 930 1011 1097 1186 1277 1358 375 t s ? 7 ? 82 ? 150 ? 225 ? 315 ? 391 ? 461 ? 526 ? 595 ? 661 ? 726 ? 786 ? 853 t h 401 466 504 569 641 718 783 863 941 1025 1106 1187 1264 400 t s ? 46 ? 98 ? 161 ? 243 ? 303 ? 384 ? 448 ? 513 ? 578 ? 643 ? 713 ? 771 ? 833 t h 385 445 503 546 604 674 748 826 890 965 1039 1110 1178 425 t s 4 ? 52 ? 110 ? 170 ? 229 ? 297 ? 394 ? 449 ? 517 ? 579 ? 641 ? 704 ? 752 t h 358 408 465 524 595 625 692 762 829 900 966 1032 1097 450 t s 11 ? 34 ? 92 ? 147 ? 209 ? 269 ? 324 ? 386 ? 446 ? 509 ? 564 ? 622 ? 672 t h 354 406 457 516 573 637 693 731 792 852 917 983 1042 475 t s ? 15 ? 51 ? 95 ? 147 ? 198 ? 255 ? 313 ? 366 ? 425 ? 480 ? 530 ? 585 ? 640 t h 355 399 451 499 556 613 675 727 779 815 873 930 988 500 t s 9 ? 28 ? 77 ? 128 ? 183 ? 233 ? 288 ? 333 ? 390 ? 438 ? 495 ? 545 ? 594 t h 313 354 399 445 500 555 615 668 726 783 825 881 934 525 t s ? 7 ? 52 ? 100 ? 147 ? 187 ? 237 ? 285 ? 335 ? 387 ? 436 ? 483 ? 530 ? 581 t h 311 356 395 438 489 537 592 645 692 746 799 850 909 550 t s ? 5 ? 39 ? 74 ? 107 ? 147 ? 192 ? 249 ? 302 ? 352 ? 397 ? 440 ? 486 ? 529 t h 300 340 378 423 468 510 560 610 659 710 756 810 865 575 t s 8 ? 28 ? 66 ? 102 ? 143 ? 181 ? 245 ? 280 ? 336 ? 366 ? 406 ? 443 ? 488 t h 312 348 379 414 453 496 544 599 654 708 759 806 847 1 table 14 shows characterization data for selected f dci frequencies. other frequencies are possible, and table 14 can be used to estimate performance. table 14 shows t he typical times for various dci clock frequencies that are required to calculate the data valid margin. the amount of margin that is available for tuning of the dsc sampling point can be determined using table 14 . maximizing the opening of the eye in both the dci and data signals improves the reliability of the data port interface. differential controlled impedance traces of equal length ( that is, delay) should be used between the host processor and the ad9142a i nput. to ensure coincident transitions with the data bits, the dci signal should be implemented as an additional data line with an alternating (010101) bit sequence from the same output drivers used for the data. the dci signal is ac - coupled by default ; thus, removing the dci signal may cause dac output chatter due to randomness on the dci input. to avoid this, it is recommended that the dac output i s disabled whenever the dci signal is not present. to do this, program the dac output current p ower down bit in r egister 0x01 , bit 7 and bit 6 to 1. when the dci signal is again present, the dac output can be enabled by setting r egister 0x01 , bit 7 and bit 6 to 0 . register 0x0d optimizes the dll stability over the operating frequency range. table 15 shows the recommended setting. table 15. dll configurat ion options dci speed register 0x0d 350 mhz 0x06 <350 mhz 0x86 the status of the dll can be polled by reading the d ata s tatus register at a ddress 0x0e . bit 0 indicates that the dll is running and attempting lock, and b it 7 is set to when the dll has locked. bit 2 is 1 when a valid d ata c lock i n is detected. the war ning bits in r egister 0x0e [6:4] can be used as indicators that the dac may be operating in a non ideal location in the delay line. note that these bits are re ad at the spi port speed, which is much slower than the actual speed of the dll. this means they can only show a snapshot of what is happening as opposed to giving real - time feedback. rev. a | page 25 of 72 ad9142a data sheet dll configuration example 1 in the following dll configuration example , f dci = 5 00 mhz, dll is enabled, and dll phase offset = 0. 1. 0x5e 0xfe /* turn off lsb delay cell*/ 2. 0x0d 0x06 /* select dll configure options */ 3. 0x0a 0xc0 /* enable dll and duty cycle correction. set dll phase offset to 0 */ 4. read 0x0e[7:4] /* expect 1000b if the dll is locked */ dll configuration example 2 in the following dll configuration example, f dci = 3 00 mhz, dll is enable, and dll phase offset = 0. 1. 0x5e 0xfe /* turn off lsb delay cell*/ 2. 0x0d 0x86 /* select dll configure options */ 3. 0x0a 0xc0 /* enable dll and duty cycle correction. set dll phase offset to 0 */ 4. read 0x0e[7:4] /* expect 1000b if the dll is locked */ parity the data interface can be continuously monitored by enabling the parity bit feature in reg ister 0x6a , bit 7 and configuring the f rame/ p arity bit as p arity by setting r egister 0x09 to 0x21. in this case, the host send s a parity bit along with each data sample. this bit is set according to the following formulas , where n is the data sample that is being checked. for even parity , xor [ frm ( n ), d0 ( n ), d1 ( n ), d2 ( n ), ..., d1 5 ( n) ] = 0 for odd p arity, xor [ frm ( n ), d0 ( n ), d1 ( n ), d2 ( n ), ..., d1 5 ( n) ] = 1 the parity bit is calculated over 17 bits (including the frame/parity bit) . if a parity error occurs, the parity error counter (register 0x6b or register 0x6c ) is incremented. parity errors on the bits sampled by the rising edge of dci increment s the r ising e dge p arity co unter (reg ister 0x6b ) and set the p ar e rrr is bit ( register 0x6a , bit 0 ). parity errors on the bits sampled by the falling edge of dci will increment the f alling e dge p arity counter (re gister 0x6c ) and set the p ar e rrf al bit ( reg ister 0x6a , bit 1 ). the parity counter continues to accumulate until it is cleared or until it reaches a maximum value of 255. the count can be cleared by writing a 1 to register 0x6a , bit 5 . to trigger a n irq when a parity error occurs , write a 1 to register 0x 0 4 , bit 7. this irq trigger s if there is either a rising e dge or f alling e dge parity error. the status of the irq can be observed via register 0x 06, bit 7 or by using the selected irq x pin . clear the irq by writing a 1 to register 0x06 , bit 7. use t he parity bit to validate the interface timing. as described p reviously , the host provide s a parity bit with the data samples , as well as configure s the ad9142a to generate an irq. the user can then sweep the sampling instance of the ad9142a input registers to determine at what point a sampling error occur s. the sampling instance can be varied in discrete increments by offsetting the nominal dll phase shift value of 90 via re gister 0x0a [3:0]. sed o peration the ad9142a provides on - chip sample error detection (sed) circuitry that simplifies verification of the input data interface. the se d compares the input data samples captured at the digital inpu t pins with a set of comparison values. the comparison values are l oaded into registers through the spi port. differences between the captured values and the com parison values are detected . opti ons are available for customizing sed test sequencing and error handling. the sed circuitry allows the application to test a short user defined pattern to confirm that the high speed source synchronous data bus is correctly implemented and meets the timing requirement. unlike the parity bit, the sed circuitry is expected to be used during initial system calibration, before the ad9142a is in use in the application. the sed circuitry operates on a data set made up of user de fined input words, denoted as i 0 , q0, i1, and q1 . the user defined pattern consists of sequential data word samples (i 0 is sampl ed on the rising edge of dci, q0 is sampled on the following falling edge of dci, i1 is sampled on the following dci rising edge , and q1 is sampled on the following dci falling edge). the user loads this data pattern in the byte format into r egister 0x61 through r egister 0x68. the depth of the user defined pattern is selectable via bit 4 in the sed_ctrl register (0x60), with the default , 0 , meaning a depth of two (using i0 and q0 ), and a 1 meaning a depth of four (using i0, q0, i1, and q1 , and requiring the use of frame signal input to define i0 to the sed state machine). to properly align the input samples using a depth of four , i 0 is indicated by asserting the frame signal for a minimum of two complete input samples as shown in figure 37 . the frame signal can be issued once at the start of the data transmission, or it can be asserted repeatedly at intervals coinciding with the s0 word . figure 37 . timing diagram of extended frame signal required to align input data for sed the sed has three flag bits (register 0x60 , bit 0, bit 1, and bit 2) that indicate the results of the input sample comparisons. the sample error det ected bit (register 0x6 0 , bit 0 ) is set when an error is detected and remains set until cleared. i 0 q 0 i 1 q 1 i 0 f r a m e data[15:0] 1 1901-137 rev. a | page 26 of 72 data sheet ad9142a the a utosample e rror d etection (aed) mode is an autoclear mode that has two effects: it activates the compare fail bit and the compare pass bit (register 0x60 , bit 1 and bit 2). the compare pass bit sets if the last comparison indicated that the sampl e was error free. the compare fail bit sets if an error is detected. the compare fail bit is automatic ally cleared by the reception of eight consecutive error - free comparisons , w hen autoclear mode is enabled. the sample error flag can be configured to trigger an irq when active, if need ed. this is done b y enabling the appropriate bit in the event flag regi ster (register 4 , b it 6 ). sed e xample normal operation the following example illustrates the ad9142a sed configuration sequence for continuously monitoring the input data and assertion of an irq when a single error is detected : 1. write to the following registers to enable the sed and load the comparison values with a 4 - deep user pattern. comparison values can be chosen arbitrarily; h owever, choosing values that require frequent bit toggling provides the most robust test. a. register 0x6 1 [7:0] i0[7:0 ] b. register 0x62 [7:0] i0[15: 8 ] c. register 0x63 [7:0] q0[7:0] d. register 0x64 [7:0] q0[15: 8 ] e. register 0x65 [7:0] i1[7:0] f. register 0x66 [7:0] i1[15: 8 ] g. register 0x67 [7:0] q1[7:0] h. register 0x68 [7:0] q1[15: 8 ] 2. enable sed. a. register 0x60 0xd0 b. register 0x60 0x90 3. enable the sed error detect flag to assert the irq x pin . a. registe r 0x04[6] = 1 4. set up frame parity as the frame signal. a. register 0x09 = 0x12 5. begin tran smitting the input data pattern ( frame signal ) is also required because the depth of the pattern is 4). delay line interface mode the dll is designed to help ease the interface timing require - ments in very high speed data rate applications. the dll has a minimum supported interface speed of 250 mhz , as shown in table 2 . for interfac e rates lower than this speed, use the interface delay line. in this mode, the dll is powered off and a four - tap delay line is provided for the user to adjust the timing between the data bus and the dci. table 16 specifies the setup and hold times for each delay tap. table 16 . delay line setup and hold times (guaranteed) d elay setting 0 1 2 3 register 0x5e[7:0] 0x00 0x80 0xf0 0x fe register 0x5f[2:0] 0x60 0x67 0x67 0x67 t s (ns) 1 ? 0.81 ? 0.97 ? 1.13 ? 1.28 t h (ns) 1.96 2.20 2.53 2.79 | t s + t h | (ns) 1.15 1.23 1.40 1.51 1 t he negative sign indicates the direction of the setup time. t he setup time is defined as positive when it is on the left side of the clock edge and negative when it is on the right side of the clock edge. there is a fixed 1.38 ns delay on the dci signal when th e delay line is enabled. each tap adds a nominal delay of 200 ps to the fixed delay. t o achieve the best timing margin, that is, to center the setup and hold window in the middle of the data eye, the user may need to add a delay on the data bus with respect to the dci in the data source. figure 38 is an example of calculating the optimal external delay. register 0x0d, bit 4 configures the dci signal coupling settings for optimal interface performance over the operating frequency range. it is recommended that this bit be set to 1 (dc - coupled dci) in the delay line interface mode. figure 38 . example of interfacing timing in the de lay line interfac e mode data eye no data transition input data [15:0] with optimized delay dci = 200mhz t delay = 0.63ns t data period = 2.5ns |t s | = 1.25ns |t h | = 2.51ns 1 1901-039 rev. a | page 27 of 72 ad9142a data sheet interface timing requirements th e following example shows how to calculate the optimal delay at the data source to achieve the best sampling timing in the delay line interface mode : ? f dci = 200 mhz ? delay s etting = 0 the shadow area in figure 38 is the interface setup and hold time window set to 0. to optimize the interface timing, this window must be p laced in the middle of the data transitions. because the input is double data rate, the available data period is 2.5 ns. therefore , the optimal data bus delay, with respect to the dci at the data source, can be calculated as ns 13 . 0 25 . 1 38 . 1 2 2 |) | | (| = ? = ? + = period data h s delay t t t t spi s e quence to enable delay line interface mode use the following spi sequence to enable the delay line interface mode: 1. [ ( : [ & r q i l j x u h w k h g h o d \ setting */ 2. [ ) : [ 3. [ ' : [ ' & f r x s o h ' & , 4. [ $ : [ 7 x u q r i i ' / / d q g g x w \ cycle correction */ rev. a | page 28 of 72 data sheet ad9142a fifo operation as is described in the data interface section, the ad9142a adopts s ource s ynchronous clocking in the data receiver. the nature of source synchronous clocking is the creation of a separate clock domain at the receiving device . in the dac, it is the dac clock domain, that is , the dacclk. therefore, there are two clock domains inside of the dac : the dci and the dacclk. o ften , these two clock domains are n ot synchronous , requiring an addi tional stage to adjus t the timing for proper data transfer. in the ad9142a , a fifo stage is inserted between the dci and dacclk domai n s to transfer the received data into the core clock domain (dacclk) of the dac. the ad9142a contains a 2 - channel, 16 - bi t wide, 8 - word deep fifo. the fifo acts as a buffer that absorbs timing variati ons between the two clock domains. the timing budget between the two clock domains in the system is significantly relaxed due to the depth of the fifo. figure 39 shows the block diagram of the datapath through the fifo. the input data is latched into the device, formatted, and then written into the fifo register , which is determined by the fifo write pointer. the v alue of the write pointer is incremented every time a new word is loaded into the fifo. meanwhile, data is read from the fifo register , which is determined by the read pointer , and fed into the digital datapath. the value of the read pointer is incremented every time data is read into the datapath from the fifo. the fifo pointers are incremented at the data rate , which is the dacclk rate divided by the interpolation rate . valid data is transmitted through the fifo as long as the fifo does not overflow (full ) or underflow ( empty ) . an overflow or underflow condition occurs when the write pointer and read pointer point to the same fifo slot . this simultaneous access of data leads to unreliable data transfer through the fifo and must be avoided. normally , data is written to and read from the fifo at the same rate to maintain a constant fifo depth. if data is written to the fifo faster than data is read, the fifo depth increases. if data is read from the fifo faster than data is written to it , the f ifo depth decr eases. for optimal timing margin, maintain the fifo depth near half full (a difference of four between the write pointer and read pointer values). the fifo depth represents the fifo pipeline delay and is part of the overall latency of the ad9142a . figure 39 . block diagram of fifo data receiver i data path q data path i dac dci input data[15:0] frame retimed dci spi fifo reset reg 0x25[0] int dacclk fifo level request register 0x23 q dac fifo write clock fifo read clock write pointer read pointer fifo slot 0 fifo slot 1 fifo slot 2 fifo slot 3 fifo slot 4 fifo slot 5 fifo slot 6 fifo slot 7 fifo level reset logic fifo data format i[15:0] i[15:0] q[15:0] q[15:0] i/q[31:0] latched data[15:0] 1 1901-040 rev. a | page 29 of 72 ad9142a data sheet resetting the fifo upon power - on of the device , the read and write pointer s start to roll around the fifo from an arbitrary slot ; consequently, the fifo depth is unknown. to avoid a concurrent read and write to the same fifo address and to assure a fixed pipeline delay from power - o n to powe r - on , it is important to reset the fifo pointers to a known state each time the device powers on or wakes up. this state is specified in t he requested fifo level (fifo depth and fifo level are used interchangeably in this d ata sheet ), which consists of two sections : the integer fifo level and the fractional fifo level. the integer fifo level represents the difference of the states bet ween the read and write point s in the unit of an input data period (1/ f data ). the fractional fifo level represents the difference of the fifo pointers that is smaller than the input data period. the resolution of the fractional fifo level is the input data period divided by the interpolation ratio and , thus , it is equal to one dacclk cycle. the exact fifo level, that is , the fifo latency, can be calculated by fifo latency = integer level + fractional level because the fifo has eight data slots, there are eight possible fifo integer levels. the max imum supported interpolation rate in the ad9142a is 8 interpolation. therefore, there are eight possible fifo fractional levels. two 3 - bit registers in register 0x23 are assigned to represent the two fifo levels , as follows: ? b its[6:4] represent the fifo integer level ? b its[2:0] repre sent the fifo fractional level. for example, if the interpolation rate is 4 and the total fifo depth is 4.5 input data periods, set the fifo_level_config ( register 0x23) to 0x42 (4 here means four data cycles and 2 means two dac cycles, which is half of a data cycle ) . note that there are only four possible fractional levels in the case of 4 interpolation . table 17 shows additional examples of configuring the fifo level in various interpolation rate modes. table 17. examples of fifo level configuration interpolation rate exampl e fifo l evel (1/ f data ) integ er level ( reg . 0x23[6:4]) fractional level ( reg . 0x23[2:0]) 2 3 + 1/2 3 1 4 4 + 1/4 4 1 8 4 + 3/8 4 3 by defau lt, th e fifo level is 4.0. it can be programmed to any allowed value from 0.0 to 7.x. the max imum allowed number for x is the interpolation rate minus 1. for example, in 8 interpolation, the max imum value allowed for x is 7. the following two ways are used to reset the fifo and initialize the fifo level : ? serial p ort (spi) initiated fifo r eset. ? f ram e initiated fifo r eset . serial port initiate d fifo reset a spi in itiated fifo reset is the most common method to reset the fifo. to initialize the fifo level through the serial port, toggle fifo_spi_reset_request ( register 0x 25[0]) from 0 to 1 and back to 0 . when the write to this register is complete, the fifo level is initialized to the request ed fifo level and the readback of fifo_spi_reset_ack ( register 0x 25[1]) is set to 1 . the fifo level readback, in the same format as the fifo level request, sho uld be within 1 dacclk cycle of the requested level. for example, if the requested value is 0x4 0 in 4 interpolation, the readback value should be one of the following : 0x33, 0x40, or 0x41. the range of 1 dacclk cycle indicates the default dac latency u ncertainty from power - on to power - on without turning on synchronization. the recommended procedure for a serial port fifo r eset is as follows: 1. configure the dac in the desired interpolation mode ( register 0x28[1:0]). 2. ens ure that the dacclk and dci are running and stable at the clock inputs. 3. program register 0x23 to the customized value , if the desired value is not 0x40. 4. request the fifo leve l reset by setting register 0x25[0] to 1. 5. verify that the device acknowledges the request by setting register 0x25[1] to 1. 6. remove the request by setting register 0x25[0] to 0. 7. ver if y t h at th e device drops the acknowledge signal by setting register 0x 25[1] to 0. 8. read back register 0x24 multiple times to verify that the actual fifo level is set to the requested level and that the readback values are stable. by design, the readback is within 1 dacclk around the requested level. f rame initiated fifo reset the frame input has two functions. one function is to indicate the beginning of a byte stream in the byte interface mode , as discussed in the data interface section. the other function is to initialize the fifo level by asserti ng the frame signal high for at least the time interval required to load complete data to the i and q dacs. this corresponds to one dci period in word interface mode and two dci periods in byte interface mode. note that this requirement of the frame pulse length is longer than that of the frame signal when it serves only to assemble the byte st r eam. the device accepts either a continuous frame or a one shot frame signal. in the continuous reset mode, the fifo responds to every valid frame pulse and resets itself. in the one shot reset mode, the fifo responds only to the first valid frame pulse after the frame_reset_mode bits (register 0x22[1:0]) are set. therefore, even with a continuous frame input, the fifo reset s one time only ; t his prevents the fifo from toggling between the two states from periodic resets. t he one shot frame reset mode is the default and the recommended mode. rev. a | page 30 of 72 data sheet ad9142a the recommended procedure for a frame i nitiated fifo r eset is as follows: 1. configure the dac in the desir ed interpolation mode ( register 0x28[1:0]). 2. en sure that the dacclk and dci are running and stable at the clock inputs. 3. e nsure that t he dll is locked (if using dll m ode) or the dci clock is being sent properly (if using bypass m ode). program registe r 0x23 t o the customized value , if the desired value is not 0x40. 4. configure the frame_reset_mode bits (register 0x22 , bits [ 1:0]) to 00b . 5. choose whether to use continuous or one shot mod e by writing 0 or 1 to en_con_frame_reset ( register 0x22 , bit 2). 6. toggle the frame input from 0 to 1 and back to 0 . the pulse width needs to be longer than the minimum requirement. a. if the frame input is a continuous clock, turn on the signal. 7. read back register 0x24 multiple times to verify that the actual fifo level is set to the requested level and the readback values are stable. by design, the readback is within 1 dacclk around the requested level. monitoring the fifo status the real - time fifo status can be monitored from the spi register 0x24 and reflects the real - time fifo depth after a fifo reset . without timing drifts in the sy stem, this readback does not change from that which resulted from the fifo reset. when there is a timing drift or ot her abnormal clocking situation , the fifo level readback can change. however , as long as the fifo does not overflow or underflow, there is no error in data trans - mission. three status bits in register 0x06, b its [2: 0 ], indicate if there are fifo underflows, overflows, or similar situations. the status of the three bits can be latched and used to trigger hardware interrupts, irq 1 and irq2 . to e nable latching and interrupts , configure the corresponding bits in register 0x03 and register 0x04 . rev. a | page 31 of 72 ad9142a data sheet rev. a | page 32 of 72 digital datapath figure 40. block diagram of digital datapath the block diagram in figure 40 shows the functionality of the digital datapath. the digital processing includes ? an input power detection block ? three half-band interpolation filters ? a quadrature modulator consisting of a fine resolution nco and an f s /4 coarse modulation block ? an inverse sinc filter ? a gain and phase and offset adjustment block the interpolation filters accept i and q data streams and process them as two independent data streams, whereas the quadrature modulator and phase adjustment block accepts i and q data streams as a quadrature data stream. therefore, quadrature input data is required when digital modulation and phase adjustment functions are used. interpolation filters the transmit path contains three interpolation filters. each of the three interpolation filters provides a 2 increase in output data rate and a low-pass function. the half-band (hb) filters are cas- caded to provide 4 or 8 interpolation ratios. the ad9142a provides three interpolation modes (see table 6). each mode offers a different usable signal bandwidth in an operating mode. which mode to select depends on the required signal bandwidth and the dac update rate. refer to table 6 for the maximum speed and signal bandwidth of each interpolation mode. the usable bandwidth is defined as the frequency band over which the filters have a pass-band ripple of less than 0.001 db and a stop band rejection of greater than 85 db. 2 interpolation mode figure 41 and figure 42 show the pass-band and all-band filter response for 2 mode. note that the transition from the transition band to the stop band is much sharper than the tran- sition from the pass band to the transition band. therefore, when the desired output signal moves out of the defined pass band, the signal image, which is supposed to be suppressed by the stop band, grows faster than the droop of the signal itself due to the degraded pass-band flatness. in cases where the degraded image rejection is acceptable or can be compensated by the analog low-pass filter at the dac output, it is possible to let the output signal extend beyond the specified usable signal bandwidth. figure 41. pass-band detail of 2 mode figure 42. all-band response of 2 mode input power detection and protection hb1 hb2 hb3 inv sinc digital gain and phase and offset adjustment coarse and fine modulation 11901-041 0.02 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0 0.050.100.150.200.250.300.350.400.45 magnitude (db) frequency (hz) 11901-042 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 00.4 0.2 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 magnitude (db) frequency (hz) 11901-043 data sheet ad9142a 4 interpolation mode figure 43 and figure 44 show the pass - band and all - band filter respons e s for 4 mode . figure 43 . pass - band d etail of 4 mode figure 44 . all - band response of 4 mode 8 interpolation mode figure 45 and figure 46 show the pass - band and all - band filter response s for 8 mode . the max imum dac update rate is 1.6 ghz , and the max imum input data rate that is supported in this mode is 200 mhz (1.6 ghz/8). figure 45 . pass - band d etail of 8 mode figure 46 . all - band response of 8 mode table 18 . half - band filter 1 coefficient lower coefficient upper coefficient integer value h(1) h(55) ? 4 h(2) h(54) 0 h(3) h(53) +13 h(4) h(52) 0 h(5) h(51) ? 3 2 h(6) h(50) 0 h(7) h(49) +69 h(8) h(48) 0 h(9) h(47) ? 134 h(10) h(46) 0 h(11) h(45) +239 h(12) h(44) 0 h(13) h(43) ? 401 h(14) h(42) 0 h(15) h(41) +642 h(16) h(40) 0 h(17) h(39) ? 994 h(18) h(38) 0 h(19) h(37) +1512 h(20) h(36) 0 h(21) h(35) ? 2307 h(22) h(34) 0 h(23) h(33) +3665 h(24) h(32) 0 h(25) h(31) ? 6638 h(26) h(30) 0 h(27) h(29) +20,754 h(28) +32,768 0.02 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 magnitude (db) frequency (hz) 1 1901-046 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 0.4 0.2 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 magnitude (db) frequency (hz) 1 1901-047 0.02 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 magnitude (db) frequency (hz) 1 1901-048 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 0.4 0.2 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 magnitude (db) frequency (hz) 1 1901-049 rev. a | page 33 of 72 ad9142a data sheet rev. a | page 34 of 72 table 19. half-band filter 2 coefficient lower coefficient upper coefficient integer value h(1) h(23) ?2 h(2) h(22) 0 h(3) h(21) +17 h(4) h(20) 0 h(5) h(19) ?75 h(6) h(18) 0 h(7) h(17) +238 h(8) h(16) 0 h(9) h(15) ?660 h(10) h(14) 0 h(11) h(13) +2530 h(12) +4096 table 20. half-band filter 3 coefficient lower coefficient upper coefficient integer value h(1) h(11) +29 h(2) h(10) 0 h(3) h(9) ?214 h(4) h(8) 0 h(5) h(7) +1209 h(6) +2048 digital modulation the ad9142a provides two modes to modulate the baseband quadrature signal to the desired dac output frequency. ? coarse (f s /4) modulation ? fine (nco) modulation f s /4 modulation the f s /4 modulation is a convenient and low power modulation mode to translate the input baseband frequency to a fixed f s /4 if frequency, f s being the dac sampling rate. when modulation frequencies other than this frequency are required, the nco modulation mode must be used. nco modulation the nco modulation mode makes use of a numerically controlled oscillator (nco), a phase shifter, and a complex modulator to provide a means for modulating the signal by a programmable carrier signal. a block diagram of the digital modulator is shown in figure 47. the nco modulation allows the dac output signal to be placed anywhere in the output spectrum with very fine frequency resolution. figure 47. nco modulator block diagram the nco modulator mixes the carrier signal generated by the nco with the i and q signals. the nco produces a quadrature carrier signal to translate the input signal to a new center frequency. a complex carrier signal is a pair of sinusoidal waveforms of the same frequency, offset 90 from each other. the frequency of the complex carrier signal is set via nco_ftw3 to nco_ftw0 in register 0x31 through register 0x34. the nco operating frequency, f nco , is always equal to f dac , the dacclk frequency. the frequency of the complex carrier signal can be set from dc up to 0.5 f nco . the frequency tuning word (ftw) is in twos complement format. it can be calculated as 2 2 dac carrier dac f f f ??? ?? ?? 0 2 32 ? ?? carrier dac carrier f f f ftw ?? 0 )() 1( ? ? ?? carrier dac carrier f f f ftw 32 2 the generated quadrature carrier signal is mixed with the i and q data. the quadrature products are then summed into the i and q data paths, as shown in figure 47. updating the frequency tuning word the frequency tuning word registers are not updated immediately upon writing, as are other configuration registers. similar to fifo reset, the nco update can be triggered in two ways. ? spi initiated update ? frame initiated update cosine sine ~ i data in q data in i data out q data out ftw[31:0] nco phase[15:0] 11901-050 data sheet ad9142a spi i nitiated u pdate in th e spi initiated update method, the user simply toggles register 0x30[0] (nco_spi_update_req) after configuring the nco settings. the nco is updated on the rising edge ( from 0 to 1 ) in this bit. register 0x30[1] (nco_spi_update_ack) goes high when the nco is updated. a falling edge ( from 1 to 0) in register 0x30[0] clea rs bit 1 of register 0x30 and prepares the nco for the next update operation. this update method is recommended when there is no requirement to align the dac output from multiple devices because spi writes to multiple devices are asynchronous. f rame initia ted update when the da c output from multiple devices must be well aligned with nco turned on, the frame initiated update is recommended. in this method, the nco s from multiple devices are updated at the same time upon the rising edge of the frame signal. to use this update method, the frame_reset_mode ( register 0x22[1:0]) must be set in nco only or fifo and nco, depending on whether a fifo reset is needed at the same time. the second step is to en sure that the reset mode is in one shot mode ( en_co n_frame_reset, register 0x22[2] = 0). when this is completed , the nco waits for a valid frame pulse and updates the ftw accordingly. the user can verify if the frame pulse is correctly received by reading register 0x30[6] (nco_frame_ update_ack) wherein a 1 indicates a complete update operation. see the fifo operation section for information to generate a valid frame pulse. datapath configurati on config uring the ad9142a datapath starts with the following four parameters: ? t he application requirements of the input data rate ? t he interpolation ratio ? th e output signal center frequency ? the output signal bandwidth given these four parameters, the first step to configur e the datapath is to verify that the device supports the desired input data rate, the dac sampling rate , and the bandwidth requirements . a fter this verification , t he modes of the interpolation filters can be chosen. if the output signal center frequency is different from the baseband input center frequency, additional frequency offset requirements are determined and applied with on - chip digi tal modulation. digital quadrature g ain and phase adjustment the digital quadrature gain and phase adjustment function enable s compensation of the gain and phase imbalance of the i and q paths caused by analog mismatches between dac i/q outputs, quadrature modulator i/q baseband inputs , and dac/modulator interface i/q paths. the undesired imbalances cause unwanted sideband signal to appear at the quadrature modulator output with significant energy. tuning the quadrature gain and phase adjust values optimize s image rejection in single sideband radios. quadrature gain adjustment ordinarily, the i and q channels have the same gain or signal magnitude . the quadrature gain adjustment is used to balance the gain between the i and q channels. the digital gain of th e i and q channels can be adjusted independently through two 6 - bit registers , idac_gain_adj ( register 0x3f[5:0]) and q dac_gain_adj ( register 0x40[5:0]). t he range of the adjustment is [ 0 , 2] or [ ? , 6 db] with a step size of 2 ? 5 ( ? 30 db). the default setting is 0x20, corresponding to a gain equal to 1 or 0 db. quadrature phase adjustment under normal circumstances, i and q channels have an angle of precisely 90 between them. the quadrature phase adjustment is used to change the angle between the i an d q channels. iq_phase_adj _msb and iq_phase_adj_lsb ( register 0x37 , bits [7:0] and register 0x38 , bits [4:0] ) provide an adjustment range of 14 with a resolution of 0.0035 . i f the original angle is precisely 90 , setting iq_phase_adj _msb and iq_phase_adj _lsb to 0x0fff adds approximately 14 between i and q dac output s , creating an angle of 104 between the channels . likewise, if the original angle is precisely 90 , setting iq_phase_adj _msb and iq_phase_adj _lsb to 0x1000 adds approximately ? 14 between the i and q dac output s , creating an angle of 76 between the channels . dc offset a djustment the dc value of the i datapath and the q datapath can be controlled i ndependently by adjusting the values in the two idac dc offset 16- bit registers, idac_ dc_offset _lsb, idac_dc_offset_msb, q dac_dc_offset _lsb, and q dac_dc_offset _msb ( register 0x3b through register 0 x3e ) . these values are added directly to the datapath values. ta ke c are not to overrange the transmitted values. as sh own in figure 48 , the dac offset current varies as a function of the i/qdac dc offset values. figure 48 shows the nominal current of the positive node of the dac output, i outp , when t he digital inputs are fixed at midscale (0x0000, twos complement data format) and the dac offset value is swept from 0x0000 to 0xffff . bec ause i outp and i outn are complementary current outputs, the sum of i outp and i outn is always 20 ma. figure 48 . dac output currents vs. dac offset value 0x0000 0x4000 0x8000 0xc000 0xffff 5 10 15 20 5 10 15 20 0 0 dac offset value i outxn (ma) i outxp (ma) 1 1901-051 rev. a | page 35 of 72 ad9142a data sheet rev. a | page 36 of 72 inverse sinc filter the ad9142a provides a digital inverse sinc filter to compensate for the dac roll-off over frequency. the inverse sinc (sinc ?1 ) filter is a seven-tap fir filter. figure 49 shows the frequency response of sin(x)/x roll-off, the inverse sinc filter, and their composite response. the composite response has less than 0.05 db pass-band ripple up to a frequency of 0.4 f dac . to provide the necessary peaking at the upper end of the pass band, the inverse sinc filter has an intrinsic insertion loss of about 3.8 db. the loss of the digital gain can be offset by increasing the quadrature gain adjustment setting on both the i and q data paths to minimize the impact on the output signal-to-noise ratio. how- ever, care is needed to ensure that the additional digital gain does not cause signal saturation, especially at high output frequencies. the sinc ?1 filter is disabled by default; it can be enabled by setting the invsinc_enable bit to 1 in register 0x27[7]). figure 49. responses of sin(x)/x roll off (blue), the sinc ?1 filter (red), and composite of both (black) table 21. inverse sinc filter lower coefficient upper coefficient integer value h(1) h(7) ?1 h(2) h(6) +4 h(3) h(5) ?16 h(4) +192 input signal power detection and protection the input signal power detection and protection function detects the average power of the dac input signal and prevents overrange signals from being passed to the next stage. an overrange dac output signal can cause destructive breakdown on power sensitive devices, such as power amplifiers. the power detection and protection feature of the ad9142a detects overrange signals in the dac. when an overrange signal is detected, the protection function either attenuates or mutes the signal to protect the downstream devices from abnormal power surges in the signal. figure 50 shows the block diagram of the power detection and protection function. the protection block is at the very last stage of the data path and the detection block uses a separate path from the data path. the design of the detection block guarantees that the worst-case latency of power detecting is shorter than that of the data path. this ensures that the protection circuit initiates before the overrange signal reaches the analog dac core. the sum of i 2 and q 2 is calculated as a representation of the input signal power. only the upper six msbs, d[15:10], of data samples are used in the calculation; consequently, samples whose power is 36 db below the full-scale peak power are not detected. the calculated sample power numbers accumulate through a moving average filter. its output is the average of the input signal power in a certain number of data clock cycles. the length of the filter is configurable through the sample_window_length (register 0x2b[3:0]). to determine whether the input average power is over range, the device averages the power of the samples in the filter and compares the average power with a user defined threshold, threshold_level_request_lsb and threshold_level_request_msb (register 0x29[7:0] and register 0x2a[4:0]). when the output of the averaging filter is larger than the threshold, the dac output is either attenuated or muted. the appropriate filter length and average power threshold for effective protection are application dependent. it is recommended that experiments be performed with real-world vectors to determine the values of these parameters. figure 50. block diagram of input signal power detection and protection function 1 ?5 ?4 ?3 ?2 ?1 0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.50 0.45 magnitude (db) frequency (hz) 11901-052 averaging filter signal processing engine power protection (attenuate or mute) dac core filter length settings reg 0x2b[3:0] user defined threshold reg 0x29[7:0] and reg 0x2a[4:0] avg power reg 0x2c[7:0] and reg 0x2d[4:0] power detection fifo i 2 + q 2 11901-053 data sheet ad9142a transmit e nable f unction the transmit enable (txen) function provides the user with a hardware switch of the dac output. the function accepts a cmos signal via pin 6 (txen). when this signal is detec ted high, the transmit path is enabled and the dac transmits the data normally. when this signal is detected low, one of the three act ions related to the dac output is triggered. this can be configured in register 0x43. 1. the dac output is gradually attenuat ed from full scale gain to 0. the attenuation step size is set in reg ister 0x42[5:0]. 2. the dac is put in sleep mod e and th e output current is turned off. other areas of the dac are still running in this mode. 3. the dac is put in power - down mode. in this mode , not only the dac output current is turned off but the rest of the dac is powered down. this minimizes the power consumption of the dac when the data is not transmitting but it takes a bit longer than the first two modes to start to retransmit data due to the device power - up time. the txen function also provides a gain ramp - up function that lets the user turn on the dac output gradually when the txen signal switches from low to high. the ramp - up gain step can be configured using reg ister 0x41[5:0]. digit al function configur ation each of the digital gain and phase adjust functions and the i nverse sinc filter can be enabled and adjusted independently . the pipeline latencies these blocks add into the data path are different between enabled and disabled . if fixed dac pipeline latency is desired during operation, leave these functions always on or always off after initial configuration. the digital dc adjust function is always on. the default value is 0; that is, there is no additional dc offset. the pipe line latency that this block adds is a constant , no matter the value of the dc offset. there is also a latency difference between using and not using the input signal power detection and protection function. therefore, to keep the overall latency fixed, le ave this function always on or always off after the initial configuration. rev. a | page 37 of 72 ad9142a data sheet multi d evice synchronizatio n and f ixed l atency a dac introduces a variation of pipeline latency to a system. the latency varia tion causes the phase of a dac output to vary from power - on to power - on. therefore, the output from different dac devices may not be perfectly aligned even with well aligned clocks and digital inputs. the skew between multiple dac outputs varies from power - on to power - on. in applications such as tr ansmit diversity or digital pre distortion , where deterministic latency is desired, the variatio n of the pipeline latency must be minimized. deterministic latency in this d ata sheet is defined as a fixed time delay from the digital input to the analog output in a dac from power - on to power - on. multiple dac devices are considered synchronized to each other when e ach dac in this group has the same constant latency from power - on to power - on. three conditions must be identical in all of the ready - to - sync devices before these devi ces are considered synchronized: ? the phase of dac internal clocks ? the fifo level ? the alignment of the input data very small inherent l atency variation the innovative architecture of the ad9142a minimizes the inherent latency variation. the worst - case variation in the ad9142a is two dac clock cycles. for example, in the case of a 1.5 ghz sample rate, the variation is less than 1.4 ns in any scenario. therefore, without turning on the synchronization engine, the dac outputs from mu ltiple ad9142a devices are guaranteed to be aligned within two dac clock cycles , regardless of the timing between the dci and the dacclk. no additional clocks are required to achieve this accuracy. the user must reset the fifo in each dac device through the spi at startup. therefore, the ad9142a can decrease the complexity of system design in multitransmit channel applications. note the alignment of the dci signals in the design . the dci is used as a reference in the ad9142a design to align the fifo and the phase of internal clocks in multiple device s. the achieved dac output alignment depends on how well the dci signal s are aligned at th e input of each device. the following e quation is the expression of the worst - case dac output alignment accuracy in the case of dci signal mismatches. t sk (out) = t sk ( dci ) + 2/ f dac where: t sk (out) is the worst - case skew between the dac output from two ad9142a devices . t sk (dci) is the skew between two dci signal s at the dci input of the two ad9142a devices . f dac is the dacclk frequency. the better the alignment of the dci signal s, the smaller is the overall skew between two dac outputs . further reducing the latency variation for applications that require finer synchronization accuracy (dac latency variation < 2 dac clock cycles), the ad9142a has a provision for enabling m ultiple devices to be synchronized to each other within a single dac clock cycle. t o further reduce the latency variation in the dac, the synchronization machine needs to be turned on and two external clocks (frame and sync) need to be generated in the sys tem and fed to all the dac devices. set up and hold timing requirement the sync clock (f sync ) serves as a reference clock in the system to reset the clock generation circuitry in multiple ad9142a devices simultaneously . inside the dac, the sync clock is sampled by the dacclk to generate a reference point for aligning the internal clocks , so there is a setup and hold timing requirement between the sync clock and the dac clock. if the user adopt s the continuous frame reset mode, that is, the fifo and sy nc engine periodically reset, the timing requirements between the sync clock and the dac clock must be met . o therwise , the device can lose lock and corrupt the output . in the one shot frame reset mode, it is still recommended that this timing be met at the time when the sync routine is run because not meeting the timing can degrade the sync alig nment accuracy by one dac cycle, as shown in table 22 . for users who want to synchronize the device in a one - shot manner and continue to monitor the synchronization status, the ad9142a provides a sync monitoring mode. it provides a continuous sync and frame clock to synchronize the part once and ignore the clock cycles after the first valid frame pulse is detected. in this way, the user can monitor the sync status wi thout periodically re synchronizing the device ; t o engage the sync monitoring mode, set register 0 x22[1:0] (frame_reset_ mode) to 11b. table 22. sync clock and dac clock setup and hold times falling edge sync timing (default) max (ps) t s (ns) 324 t h (ns) 1 ? 92 | t s + t h | (ns) 232 1 the negative sign indicates the direction of the setup time. the setup time is defined as positive when it is on the left side of the clock edge and negative when it is on the right side of the clock edge. rev. a | page 38 of 72 data sheet ad9142a synchronization impl ementation the ad9142a lets the user choose either the rising or falling edge of the dac clock to sample the sync clock, which makes it easier to meet the timing requirements. ensure that the sync clock , f sync , is 1/8 f data or slower by a factor of 2n, n being an integer (1, 2, 3 ). note that there is a limit on how slow the sync clock can be received because of the ac coupling nature of the sync clock receiver. choose a n appropriate value of the ac coupling ca pacitors to ensure that the signal swing meets the data sheet specification , as listed in table 2 . the frame clock reset s the fifo in multiple ad9142a devices. the frame can be eithe r a one shot or continuous clock. in either case , the pulse width of the frame must be longer than one dci cycle in the word interface mode and two dci cycles in the byte interface mode. when the frame is a continuous clock, f frame , ensure that it is 1/8 f data or slower by a factor of 2n, n being an integer (1, 2, 3 ). table 23 lists the requirements of the frame clock in various conditions. byte interface mode is not supported when the frame signal is used in synchronization. table 23. f rame clock speed and pulse width requirement sync c lock max imum s peed minimum pulse width one shot n/a 1 for both one shot and continuous sync clocks , w ord interface mode = one dci cycle and b yte interface mode = two dci cycles . continuous f data /8 1 n/a means not applicable. synchronization p rocedures when the sync accuracy of an application is l ess precise than two dac clock cycles, it is recommended to turn off the synchro - nization machine because there are no additional steps required, other than the regular start - up procedure sequence. for applications that require more precise sync accuracy than two dac clock cycle s , it is recommended that the procedure in the synchronization procedure for pll off or synchronization procedure for pll on sections be followed to set up the system and configur e the device. for more information about the details of the synchronization scheme in the ad9142a and using the synchronization function to correct system skews and drifts, see the dac latency a nd system skews section . synchronization p rocedure for pll off 1. configure the dac interpolation mode and , if nco is used, configure the nco ftw. 2. set up the dac data interface according to the procedure outlined in the data interface section a nd verify that the dll is locked. 3. choose the appropriate mode in the frame_reset_mode bits (register 0x22[1:0]) . a. if nco is not used, choose fifo only mode. b. if nco is used, it must be synchronized. fifo and nco mode can then be used. 4. configure b it 2 in register 0 x22 for continuous or one shot reset mode. one shot reset mode is recommended. 5. ensur e that the dacclk, dci, and sync clock to all of the ad9142a devices are running and stable . 6. enable the sync engine by writing 1 to register 0 x21[0]. 7. send a valid frame pulse(s) to all of the ad9142a devices. 8. ver if y that the frame pulse is received by each device by reading back register 0 x22[3]. all the readback values are 1 . at this point, t he devices should be synchronized. synchronization p rocedure for pll on note that , because the sync clock and pll reference clock share the same clock and the max imum sync clock rate is f data /8, the same limit also applies to the reference clock. theref ore , only 2 interpolation is supported for synchronization with pll on . 1. set up the pll according to the procedure in the clock multiplication section and e nsure that the pll is l ocked. 2. configure the dac interpolation mode and , if nco is used, configure the nco ftw. 3. set up the dac data interface according to the procedure in the data interface section and verify that the dll is locked. 4. choose the appropriate mode in the frame_reset_mode bits (register 0x22[1:0]) a. if nco is not used, choose the fifo only mode. b. if nco is used, it must be synchronized. fifo and nco mode can then be used. 5. configure b it 2 in register 0 x22 for continuous or one shot reset mode. one shot reset mode is recommended. 6. ensure that dacclk, dci, and sync clock to all of the ad9142a devices are running . 7. enable the sync engine by writing 1 to register 0 x21[0]. 8. send a valid frame pulse(s) to all of the ad9142a devices. 9. ver if y that the frame pulse is received by each device by reading back register 0 x22[3]. all the readback values are 1 . at this point, t he devices should be synchronized. rev. a | page 39 of 72 ad9142a data sheet rev. a | page 40 of 72 interrupt request operation the ad9142a provides an interrupt request output signal on pin 50 and pin 51 ( irq2 and irq1 , respectively) that can be used to notify an external host processor of significant device events. upon assertion of the interrupt, query the device to determine the precise event that occurred. the irq1 pin is an open-drain, active low output. pull the irq1 pin high external to the device. this pin can be tied to the interrupt pins of other devices with open-drain outputs to wire-or these pins together. ten event flags provide visibility into the device. these flags are located in the two event flag registers, register 0x05 and register 0x06. the behavior of each event flag is independently selected in the interrupt enable registers, register 0x03 and register 0x04. when the flag interrupt enable is active, the event flag latches and triggers an external interrupt. when the flag interrupt is disabled, the event flag monitors the source signal, but the irq1 and irq2 pins remain inactive. interrupt working mechanism figure 51 shows the interrupt related circuitry and how the event flag signals propagate to the irqx output. the interrupt_ enable signal represents one bit from the interrupt enable register. the event_flag_source signal represents one bit from the event flag register. the event_flag_source signal represents one of the device signals that can be monitored, such as the pll_lock signal from the pll phase detector or the fifo_warning_1 signal from the fifo controller. when an interrupt enable bit is set high, the corresponding event flag bit reflects a positively tripped version of the event_flag_ source signal; that is, the event flag bit is latched on the rising edge of the event_flag_source signal. this signal also asserts the external irq pins. when an interrupt enable bit is set low, the event flag bit reflects the present status of the event_flag_source signal, and the event flag has no effect on the external irq pins. clear the latched version of an event flag (the interrupt_ source signal) in one of two ways. the recommended method is by writing 1 to the corresponding event flag bit. the second method is to use a hardware or software reset to clear the interrupt_source signal. the irq2 circuitry works in the same way as the irq1 circuitry. any one or multiple event flags can be enabled to trigger the irq1 and irq2 pins. the user can select one or both hardware interrupt pins for the enabled event flags. register 0x07 and register 0x08 determine the pin to which each event flag is routed. set register 0x07 and register 0x08 to 0 for irq1 and set these registers to 1 for irq2 . interrupt service routine interrupt request management starts by selecting the set of event flags that require host intervention or monitoring. enable the events that require host action so that the host is notified when they occur. for events requiring host intervention upon irqx activation, run the following routine to clear an interrupt request: 1. read the status of the event flag bits that are being monitored. 2. set the interrupt enable bit low so that the unlatched event_flag_source signal can be monitored directly. 3. perform any actions that may be required to clear the event_flag_source signal. in many cases, no specific actions may be required. 4. read the event flag to verify that the actions taken have cleared the event_flag_source signal. 5. clear the interrupt by writing 1 to the event flag bit. 6. set the interrupt enable bits of the events to be monitored. note that some event_flag_source signals are latched signals. these signals are cleared by writing to the correspon- ding event flag bit. for more information about each of the event flags, see the device configuration register map section. figure 51. simplified schematic of irq circuitry interrupt_enable event_flag_source device_reset event_flag interrupt_ source 1 0 other interrupt sources irq w rite_1_to_event_flag 11901-054 data sheet ad9142a temperature s ensor the ad9142a has a diode - based temperature sensor for measuring the temperature of the die. the temperature reading is accessed using register 0x1d and register 0x1e. the temperature of the die can be calculated as 106 ) 237 , 41 ] 0 : 15 [ ( ? = dietemp t die where t die is the die temperature in degrees celsius. the temperature accur acy is 7 c typical over the +85 c to ? 40 c range with one point temperature calibration against a known temperature . a typical plot of the die temperature code readback vs. die temperature is shown in figure 52. figure 52 . die temperature code readback vs. die te mperature estimates of the ambient temperature can be made if the power dissipation of the device is known. for example, if the device power dissipation is 800 mw and the measured die temperature is 50c, then the ambient temperature can be calculated as t a = t die C p d ja = 50 C 0.8 20.7 = 33.4 c where: t a is the ambient temperature in degrees celsius. t die is the die temperature in degrees celsius. p d is power consumption of the device. ja is the thermal resistance from junction to ambient of the ad9142a as shown in tabl e 8 . to use the temperature sensor, i t must be enabled by setting register 0x1c[0] to 1. in addition, to obtain accurate readings, set the die temperature control register (register 0x1c) to 0x03 . ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 temperature (c) die code readback 35000 37000 39000 41000 43000 45000 47000 49000 51000 1 1901-201 rev. a | page 41 of 72 ad9142a data sheet dac input clock conf igurations the ad9142a dac sample clock (dacclk) can be sourced directly or by clock multiplying. clock multiplying employs the on - chip pll that accepts a reference clock operating at a submult iple of the desired dacclk rate . the pll then multiplies the reference clock up to the desired dacclk frequency , which can then be used to generate all of the internal clocks required by the dac . the clock multiplier provides a high quality clock that m eets the performance requirements of most applications. using the on - chip clock multiplier removes the burden of generating and distributing the high speed dacclk. the second mode bypasses the clo ck multiplier circuitry and let s dacclk be sourced directly to the dac core. this mode le t s the user source a very high quality clock directly to the dac core. driving the dacclk a nd refclk inputs the dacclk x and refx/syncx dif ferential inputs share similar clock receiver input circuitry. figure 53 shows a simplified circuit diagram of the input. the on - chip clock receiver h as a differential input impedance of about 10 k?. it is self biased to a common - mode voltage of about 1.25 v. the inputs can be driven by differential pecl or lvds drivers with ac coupling between the clock source and the receiver . figure 53 . clock receiver input simplified equivalent circuit the minimum input drive lev el to the differential clock input is 1 00 mv p - p differential . the optimal performance is achieved when the clock input signal is between 800 mv p - p differential a nd 1.6 v p - p differential. whether using the on - chip clock multiplier or sourcing the dacclk directly, the input clock signal to the device must have low jitter and fast edge rates to optimize the dac noise performance. direct clocking direct clocking with a low noise clock produces the lowest noise spectral density at the dac outputs. to select the differential clk inputs as the source for the dac sampling clock, set the pll enable bit ( register 0 x 12[ 7 ] ) to 0. this powers down the internal pll clock multip lier and selects the input from the dacclkp and dacclkn pins as the source for the internal dac sampl ing clock. the refclk x input can remain floating. the device also has clock duty cycle correction circuitry and differ ential input level correction circuitry. enabling these circuits can provide improved performance in some cases. the control bits for these functions ar e in register 0 x10 and register 0 x11 . clock multiplication the on - chip pll clock multiplier circuit generate s the dac sample rate clo ck from a lower frequency reference clock. when the pll enable bit ( register 0 x12[7]) is set to 1, the clock multiplicati on circuit generates the dac sampling clock from the lower rate refx/syncx input and t he dacclk x input is left floating. the functional diagram of the clock multiplier is shown in figure 54. the clock multipli er circuit operates such that the vco outputs a frequency, f vco , equal to th e refx/syncx inp ut signal frequency multiplied by n1 n0. n1 is the divide ratio of the loop divider ; n0 is the divide ratio of the vco divider. f vco = f refclk ( n1 n0 ) the dac sample clock frequency, f dacclk , is equal to f dacclk = f refclk n1 the output frequency of the vco must be chosen to keep f vco in the optimal operating range of 1.0 3 ghz to 2. 07 ghz. it is important to select a frequency of the reference clock and values of n1 and n0 so that the desired dacclk frequency can be synthesized and the vco output frequency is in the correct range. figure 54 . pll clock multiplication circuit 1.25v 5k? 100? 5k? dacclkp/ refp/syncp ad9142a dacclkn/ refn/syncn 1~100nf 1~100nf recommended external circuitry 1 1901-055 phase frequency detection charge pump pll charge pump current reg 0x14[4:0] divide by 2, 4, 8, or 16 loop divider reg 0x15[1:0] divide by 1, 2, or 4 vco divider reg 0x15[3:2] on-chip loop filter pll loop bw reg 0x14[7:5] vco (1ghz~2.1ghz) adc vco control voltage reg 0x16[3:0] refp/syncp (pin 2) refn/syncn (pin 3) dacclkn (pin 62) dacclkp (pin 61) dacclk pll enable reg 0x12[7] 1 1901-056 rev. a | page 42 of 72 data sheet ad9142a pll settings t he pll circuitry requires three settings to be programmed to their nominal values. the pll values shown in table 24 are the recommended settings for these parameters. table 24 . pll se ttings pll spi control register register address optimal setting (binary) pll loop bandwidt h 0x14[7:5] 111 pll charge pump current 0x14 [4:0] 00111 pll cross point c ontrol e nable 0x15[4] 0 configuring the vco tuning band the pll vco has a valid operating range from approximately 1.0 3 ghz to 2.07 ghz covered in 6 4 overlapping frequency bands. for any desired vco output frequency, there may be several valid pll band select values. the frequency bands of a typical device are shown in figure 55 . device - to - device variations and operating temperature affect the actual band frequency range. therefore, it is required that the optimal pll band select v alue be determined for each individual device. automatic vco band s elect the device has an automatic vco band select feature on chip. using the automatic vco band select feature is a simple and reliable method of configuring the vco frequency band. this f eature is enabled by starting the pll in manual mode , and then placing the pll in auto band select mode by setting register 0 x12 t o a v alue of 0xc 0 and then to a value of 0x 8 0. when these values are written , the device executes an automated routine that determines the optimal vco band setting for the device. the setting selected by the device ensures that the pll remains locked over the full ?40c to +85c operating temperature range of the devi ce without f urther adjustment. the pll remains locked over the full temperature range even if the temperature during initialization is at o ne of the temperature extremes. figure 55 . pll l ock range for a typical device manual vco band sele ct the device includes a manual band select mo de (pll auto manual enable, register 0 x 12[6] = 1) that lets the user select the vco tuning band. i n manual mode, the vco band is set directly with the value written to the manual vco band bits ( register 0 x 12 [5:0]) . pll enable sequence to enable the pll in automatic or manual mode properly , the following sequence must be followed: automatic mode sequence 4. configure the loop divider and the vco divider registers for the desired divide ratios. 5. set 00111b to pll charge pump current and 111b to pll loop bandwidth for the best performance. register 0x14 = 0xe7 (default). 6. set the pll mode to ma nual using register 0x12[6] = 1 . 7. enable the pll using register 0x12[7] = 1. 8. set the pll mode to autom atic using register 0x12[6] = 0 . manual mode 1. configure the loop divider and the vco d ivider registers for the desired divide ratios. 2. set 00111b to pll charge pump current and 111 to pll loop bandwidth for the best performance. register 0x14 = 0xe7 (default). 3. select the desired band using register 0x12[5:0]. 4. set the pll mode to ma nual using register 0x12[6] = 1 . 5. enable the pll using register 0x12[7] = 1 . 61 57 53 49 45 41 37 33 29 25 21 17 13 9 5 1 950 1150 1350 1550 1750 1950 2150 pll band vco frequency (mhz) 1 1901-057 rev. a | page 43 of 72 ad9142a data sheet rev. a | page 44 of 72 analog outputs transmit dac operation figure 56 shows a simplified block diagram of the transmit path dacs. the dac core consists of a current source array, a switch core, digital control logic, and full-scale output current control. the dac full-scale output current (i outfs ) is nominally 20 ma. the output currents from the iout1p/iout2p and iout1n/ iout2n pins are complementary, meaning that the sum of the two currents always equals the full-scale current of the dac. the digital input code to the dac determines the effective differential current delivered to the load. figure 56. simplified block diagram of dac core the dac has a 1.2 v band gap reference with an output imped- ance of 5 k. the reference output voltage appears on the vref pin. when using the internal reference, decouple the vref pin to avss with a 0.1 f capacitor. use the internal reference only for external circuits that draw dc currents of 2 a or less. for dynamic loads or static loads greater than 2 a, buffer the vref pin. if desired, the internal reference can be overdriven by applying an external reference (from 1.10 v to 1.30 v) to the vref pin. a 10 k external resistor, r set , must be connected from the fsadj pin to avss. this resistor, together with the reference control amplifier, sets up the correct internal bias currents for the dac. because the full-scale current is inversely proportional to this resistor, the tolerance of r set is reflected in the full-scale output amplitude. the full-scale current equation, where the dac gain is individually set for the q and i dacs in register 0x40 and register 0x44, respectively, is as follows: ? ? ? ? ? ? ? ? ? ? ? ? ???? dac gain r v i set ref fs 16 3 72 for nominal values of v ref (1.2 v), r set (10 k), and dac gain (512), the full-scale current of the dac is typically 20 ma. the dac full-scale current can be adjusted from 8.64 ma to 31.68 ma by setting the dac gain parameter, as shown in figure 57. figure 57. dac full-scale cu rrent vs. dac gain code transmit dac transfer function the output currents from the iout1p/iout2p and iout1n/ iout2n pins are complementary, meaning that the sum of the two currents always equals the full-scale current of the dac. the digital input code to the dac determines the effective differen- tial current delivered to the load. iout1p/iout2p provide maximum output current when all bits are high. the output currents vs. daccode for the dac outputs is expressed as outfs n outp i daccode i ? ? ? ? ? ? ? ? 2 (1) i outn = i outfs C i outp (2) where daccode = 0 to 2 n ? 1. transmit dac output configurations the optimum noise and distortion performance of the ad9142a is realized when it is configured for differential operation. the common-mode rejection of a transformer or differential amplifier significantly reduces the common-mode error sources of the dac outputs. these common-mode error sources include even-order distortion products and noise. the enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude increases. this is due to the first- order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. i dac iout1p iout1n q dac iout2n iout2p current scaling i dac fs adjust reg 0x18, reg 0x19 q dac fs adjust reg 0x1a, reg 0x1b 0 .1f 10k ? r set fsadj vref 5k ? 1.2v 11901-058 35 0 01000 dac gain code i fs (ma) 30 25 20 15 10 5 200 400 600 800 11901-059 data sheet ad9142a rev. a | page 45 of 72 figure 58 shows the most basic dac output circuitry. a pair of resistors, r o , converts each of the complementary output currents to a differential voltage output, v out . because the current outputs of the dac are high impedance, the differential driving point impedance of the dac outputs, r out , is equal to 2 r o . see figure 59 for the output voltage waveforms. figure 58. basic transmit dac output circuit figure 59. output voltage waveforms the common-mode signal voltage, v cm , is calculated as o fs cm r i v ?? 2 the peak output voltage, v peak , is calculated as v peak = i fs r o in this circuit configuration, the single-ended peak voltage is the same as the peak differential output voltage. interfacing to modulators the ad9142a interfaces to the adl537x family of modulators with a minimal number of components. an example of the recommended interface circuitry is shown in figure 60. figure 60. typical interface circuitry between the ad9142a and the adl537x family of modulators the baseband inputs of the adl537x family require a dc bias of 500 mv. the nominal midscale output current on each output of the dac is 10 ma (one-half the full-scale current). therefore, a single 50 resistor to ground from each of the dac outputs results in the desired 500 mv dc common-mode bias for the inputs to the adl537x . the addition of the load resistor in parallel with the modulator inputs reduces the signal level. the peak-to-peak voltage swing of the transmitted signal is )2( )2( lb lb fs signal rr rr iv ?? ?? ?? baseband filter implementation most applications require a baseband anti-imaging filter between the dac and the modulator to filter out nyquist images and broadband dac noise. the filter can be inserted between the i-v resistors at the dac output and the signal level setting resistor across the modulator input. this configuration establishes the input and output impedances for the filter. figure 61 shows a fifth-order, low-pass filter. a common-mode choke is placed between the i-v resistors and the remainder of the filter to remove the common-mode signal produced by the dac and to prevent the common-mode signal from being converted to a differential signal, which can appear as unwanted spurious signals in the output spectrum. splitting the first filter capacitor into two and grounding the center point creates a common-mode low-pass filter, which provides additional common-mode rejection of high frequency signals. a purely differential filter can pass common-mode signals. for more details about interfacing the ad9142a dac to an iq modulator, refer to the circuits from the lab? circuit note cn-0205, interfacing the adl5375 i/q modulator to the ad9122 dual channel, 1.2 gsps high speed dac on the analog devices website. figure 61. dac modulator interface with fifth-order, low-pass filter r o r o v ip + v in ? v outi iout1p iout1n r o r o v qp + v qn ? v outq iout2p iout2n 11901-060 + v peak v cm 0 ?v peak v n v p v out 11901-061 rbip 50 ? rbin 50 ? 67 66 ibbn ibbp ad9142a adl537x rbqn 50 ? rbqp 50 ? 59 58 rli 100 ? rlq 100 ? iout1n iout1p iout2p iout2n qbbp qbbn 11901-062 ad9142a 50 ? 50 ? 33nh 33nh 3.6pf 33nh 33nh 140 ? 6pf 3pf 3pf 22pf 22pf adl537x 11901-063 ad9142a data sheet reducing lo leakage and unwanted sidebands analog quadrature modulators can introduce unwanted signals at the local oscillator ( lo) frequency due to dc offset voltages in the i and q baseband inputs, as well as feedthrough pat hs from the lo input to the out put. the lo feedthrough can be nulled by applying the correct dc offset voltages at the dac output using the digital dc o ffset adj ustments (register 0x3b through register 0x3e ). effective sideband suppression requires both gain and phase matching of the i and q signals. the i/q phase adjust registers (register 0x3 7 and register 0x38 ) and the dac fs adjust registers (register 0x18 th rough register 0x1b ) can be used to calibrate the i and q transmit paths to optimize sideband suppression. for more information about suppressing lo leakage and sideband image, refer to the an - 1039 application note , correcting imperfections in iq modulators to improve rf signal fidelity and the an - 1100 application note , wireless transmitter iq balance and sideband suppression from the analog devices w ebsite. rev. a | page 46 of 72 data sheet ad9142a example start - up routine to ensure reliable start up of the ad9 142a , certain sequences must be fo llowed . device configuration and start - up sequence 1 1. set f dci = 375 mhz, f out = 250 mhz, and interpolation to 4 . 2. disable the pll . 3. enable f ine nco and the inverse sinc filter. 4. use the dll - based interface mode with dll phase offset = 0. derived nco settings the following nco settings can be derived from the device configuration: ? f dac = 375 4 = 1500 mhz. ? f carrier = f out = 250 mhz. ? ftw = f carrier / f dac 2 32 = 0x 2aaaaaaa. start - u p sequence 1 1. power up the device (no specific power supply sequence is required). 2. apply stable dac clock. 3. apply stable dci clock. 4. feed stable input data. 5. issue hardware reset (optional). /* device configuration register write sequence */ 0x00 0x20 /* issue software reset */ 0x20 0x01 /* device s tartup c onfiguration */ /* configure d ata i nterface */ 0x5e 0xfe /* turn off lsb delay cell */ 0x0a 0xc0 /* enable the dll and duty cycle correction. set dll phase offset to 0 */ read 0x0e[7:4] /* expect 1000b if the dll is locked */ /* configure i nterpolation filter */ 0x28 0x02 /* 4 interpolation */ /* reset fifo */ 0x25 0x01 read 0x25[1] /* expect 1b if the fifo reset is complete */ read 0x24 /* the readback should be one of the three values: 0x3 3 , 0x40, or 0x41 */ /* configure nco */ 0x27 0x40 /* enable nco */ 0x31 0xaa 0x32 0xaa 0x33 0xaa 0x34 0x2a 0x30 0x01 read 0x30[1] /* expect 1b if the nco update is complete */ /* enable i nverse sinc filter */ 0x27 0xc 0 /* power up dac outputs */ 0x01 0x00 device configuration and start - up sequence 2 1. set f dci = 2 00 mhz and interpolation to 8 . 2. enable the pll, and set f ref = 2 00 mhz. 3. enable the i nverse sinc filter. 4. use the delay line - based interface mode with a delay setting of 0. deri ved pll settings the following pll settings can be derived from the device configuration: ? f dac = 200 8 = 1600 mhz. ? f vco = f dac = 1600 mhz (1 .03 ghz < f vco < 2 .07 ghz). ? vco divider = f vco /f dac = 1. ? loop divid er = f dac /f ref = 8 . start - u p sequence 2 1. power up the device (no specific power supply sequence is required). 2. apply stable dac clock. 3. apply stable dci clock. 4. feed stable input data. 5. issue hardware reset (optional). /* device configuration register write sequence */ 0x00 0x20 /* issue software reset */ 0x20 0x01 /* device s tartup c onfiguration */ /* configure pll */ 0x14 0xe7 /* configure pll loop bw and charge pump current */ 0x15 0xc2 /* configure vco divider and l oop divider */ 0x12 0xc0 /*enable the pll */ 0x12 0x80 wait 10ms for autoba nd selection to finish read 0x16[7] /* expect 1b if the pll is locked */ rev. a | page 47 of 72 ad9142a data sheet /* configure d ata i nterface */ 0x5e 0x0 0 /* configure the delay setting */ 0x5f 0x60 0x0d 0x16 /* dc couple dci */ 0x0a 0x00 /* turn off dll and duty cycle correction */ /* configure i nterpolation filter */ 0x28 0x03 /* 8 interpolation */ /* reset fifo */ 0x25 0x01 read 0x25[1] /* expect 1b if the fifo reset is complete */ read 0x24 /* the readback should be one of the three values: 0x37, 0x40, or 0x41 */ /* enable i nverse sinc filter */ 0x27 0x80 /* power up dac outputs */ 0x01 0x00 rev. a | page 48 of 72 data sheet ad9142a device configuration register map table 25 . device configura tion register map reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 common [7:0] reserved spi_lsb_ first device_ reset reserved 0x00 rw 0x01 pd_control [7:0] pd_ i dac pd_qdac pd_datarcv reserved pd_device pd_dacclk pd_frame 0xc0 rw 0x03 interrupt_ enable0 [7:0] reserved enable_ sync_lost enable_ sync_ locked enable_ sync_done enable_pll_ lost enable_pll_ locked enable_ over_ threshold enable_ dacout_ muted 0x00 rw 0x04 interrupt_ enable1 [7:0] enable_ parity_fail enable_ sed_fail enable_dll_ warning enable_ dll_locked reserved enable_fifo_ underflow enable_ fifo_ overflow enable_ fifo_ warning 0x00 rw 0x05 interrupt_ flag0 [7:0] reserved sync_lost sync_ locked sync_done pll_lost pll_locked over_ threshold dacout_ muted 0x00 r 0x06 interrupt_ flag1 [7:0] parity_fail sed_fail dll_ warning dll_locked reserved fifo_ underflow fifo_ overflow fifo_ warning 0x00 r 0x07 irq_sel0 [7:0] reserved sel_sync_ lost sel_sync_ locked sel_sync_ done sel_pll_lost sel_pll_ locked sel_ over _ threshold sel_ dacout_ muted 0x00 rw 0x08 irq_sel1 [7:0] sel_parity_ fail sel_sed_ fail sel_dll_ warning sel_dll_ locked reserved sel_ fifo_ underflow sel_ fifo_ over flow sel_fifo_ warning 0x00 rw 0x09 frame_ mode [7:0] reserved p arusage frmusage reserved frame_pin_usage 0x00 rw 0x0a data_cntr_0 [7:0] dll_enable duty_ correction_ enable reserved dll_phase_offset 0x40 rw 0x0b data_cntr_1 [7:0] clear_warn reserved 0x39 rw 0x0c data_cntr_2 [7:0] reserved 0x64 rw 0x0d data_cntr_3 [7:0] low_dci_en reserved dc_couple_ low_en reserved 0x06 rw 0x0e data_stat_0 [7:0] dll_l ock dll_w arn d ll_s tart _ w arn ing d ll_end_ w ar n ing reserved dci_on reserved dll _ r unning 0x00 r 0x10 dacclk_ receiver_ ctrl [7:0] dacclk_ dutycycle_ correction reserved dacclk_ crosspoint_ ctrl_enable dacclk_crosspoint_level 0xff rw 0x11 refclk_ receiver_ ctrl [7:0] dutycycle_ correction reserved refclk_ crosspoint_ ctrl_enable refclk_crosspoint_level 0x5f rw 0x12 pll_ctrl0 [7:0] pll_enable auto_ manual_ sel pll_manual_band 0x00 rw 0x14 pll_ctrl2 [7:0] pll_loop_bw pll_cp_current 0xe7 rw 0x15 pll_ctrl3 [7:0] diglogic_divider reserved crosspoint_ ctrl_en vco_divider loop_divider 0xc9 rw 0x16 pll_status0 [7:0] pll_lock reserved vco_ctrl_voltage_readback 0x00 r 0x17 pll_status1 [7:0] reserved pll_band_readback 0x00 r 0x18 idac_fs_ adj0 [7:0] i dac_fullscale_adjust_lsb 0xf9 rw 0x19 idac_fs_ adj1 [7:0] reserved idac_fullscale_adjust_ msb 0xe1 rw 0x1a qdac_fs_adj0 [7:0] qdac_fullscale_adjust_lsb 0xf9 rw 0x1b qdac_fs_adj1 [7:0] reserved qdac_fullscale_adjust_ msb 0x01 rw 0x1c die_temp_ sensor_ctrl [7:0] reserved fs_current ref_current die_temp_ sensor_en 0x02 rw 0x1d die_temp_ lsb [7:0] die_temp_lsb 0x00 r 0x1e die_temp_ msb [7:0] die_temp_msb 0x00 r 0x1f chip_id [7:0] chip_id 0x0a r 0x20 interrupt_ config [7:0] interrupt_configuration 0x00 rw 0x21 sync_ctrl [7:0] reserved sync_clk_ edge_sel sync_ enable 0x00 rw 0x22 frame_rst_ ctrl [7:0] reserved arm_frame en_con_ frame_reset frame_reset_mode 0x12 rw rev. a | page 49 of 72 ad9142a data sheet reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x23 fifo_level_ config [7:0] reserved integer_fifo_level_request reserved fractional_fifo_level_request 0x40 rw 0x24 fifo_level_ readback [7:0] reserved integer_fifo_level_readback reserved fractional_fifo_level_readback 0x00 r 0x25 fifo_ctrl [7:0] reserved fifo_spi_ reset_ack fifo_spi_ reset_ request 0x00 rw 0x26 data_ format [7:0] data _ format data_ pairing data_bus_ invert reserved data_bus_ width 0x00 rw 0x27 datapath_ ctrl [7:0] invsinc_ enable nco_enable iq _gain_ adj_ dcoffset_ enable iq_ phase_adj_ enable reserved fs4_ modulation_ enable nco _ sideband _ sel send_idata _to_qdac 0x00 rw 0x28 interpolation _ctrl [7:0] reserved int erpolation _mode 0x00 rw 0x29 over_ threshold_ ctrl0 [7:0] threshold_level_request _lsb 0x00 rw 0x2a over_ threshold_ ctrl 1 [7:0] reserved threshold_level_request_msb 0x00 rw 0x2b over_ threshold_ ctrl 2 [7:0] enable_ protection iq_data_ swap reserved sample_window_length 0x00 rw 0x2c input_ power_ readback_lsb [7:0] i nput_power_readback_lsb 0x00 r 0x2d i nput_power_ readback_ msb [7:0] reserved input_power_readback_msb 0x00 r 0x30 nco_ctrl [7:0] reserved nco_frame_ update_ack spi_nco_ phase_rst_ ack spi_nco_ phase_ rst_req reserved nco_spi_ update_ack nco_spi_ update_req 0x00 rw 0x31 nco_freq_ tuning_ word0 [7:0] nco_ ftw0 0x00 rw 0x32 nco_freq_ tuning_ word 1 [7:0] nco_ ftw1 0x00 rw 0x33 nco_freq_ tuning_ word 2 [7:0] nco_ ftw2 0x00 rw 0x34 nco_freq_ tuning_ word 3 [7:0] nco_ ftw3 0x10 rw 0x35 nco_phase_ offset0 [7:0] nco_phase_offset_lsb 0x00 rw 0x36 nco_phase_ offset1 [7:0] nco_phase_offset_msb 0x00 rw 0x37 iq_phase_ adj0 [7:0] iq_ phase_adj _ lsb 0x00 rw 0x38 iq_phase_ adj 1 [7:0] reserved iq_ phase_adj _msb 0x00 rw 0x39 lvds_in_ pwr_down_0 [7:0] pwr_down_data_input_bits 0x00 rw 0x3b idac_ dc_ offset0 [7:0] i dac_dc_offset_lsb 0x00 rw 0x3c idac_ dc_ offset1 [7:0] i dac_dc_offset_msb 0x00 rw 0x3d qdac_ dc_ offset0 [7:0] qdac_ dc_ offset _lsb 0x00 rw 0x3e qdac_ dc_ offset1 [7:0] qdac_ dc_ offset _msb 0x00 rw 0x3f idac_gain_ adj [7:0] reserved idac_gain_adj 0x20 rw 0x40 q dac_gain_ adj [7:0] reserved qdac_gain_adj 0x20 rw 0x41 gain_step_ ctrl0 reserved ramp_up_step 0x01 rw rev. a | page 50 of 72 data sheet ad9142a reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x42 gain_step_ ctrl 1 dac_ output_ off dac_ output _ status ramp_down_step 0x 41 rw 0x43 tx_enable_ ctrl [7:0] reserved txenable_ gainstep_en txenable_ sleep_en txenable_ power_ down_en 0x07 rw 0x44 dac_ output_ ctrl [7:0] dac_ output_ ctrl_en reserved fifo_ warning_ shutdown_ en overthreshold _shutdown_en reserved fifo_e rror_ shutdown_ en 0x8 d rw 0x5e enable_dll_ delay_cell0 [7:0] delay_cell_enable [7:0] 0xff 0x5f enable_dll_ delay_cell 1 [7:0] reserved delay_cell_enable [10:8] 0x67 rw 0x60 sed_ctrl [7:0] sed_e nable sed_e rr_ c lear aed_e nable sed_ depth reserved aed_p ass aed_f ail sed_f ail 0x00 rw 0x61 sed_patt_ l_ i 0 [7:0] sed_pattern_r ise _ i 0[7:0] 0x00 rw 0x62 sed_patt_ h _ i 0 [7:0] sed_pattern _r ise _ i 0[15:8] 0x00 rw 0x63 sed_patt_ l_ q0 [7:0] sed_pattern_f all _ q0 [7:0] 0x00 rw 0x64 sed_patt_ h _ q0 [7:0] sed_pattern _f all _ q0 [15:8] 0x00 rw 0x65 sed_patt_ l_ i1 [7:0] sed_pattern _r ise _ i1 [7:0] 0x00 rw 0x66 sed_patt_ h _ i1 [7:0] sed_pattern _r ise _ i1 [15:8] 0x00 rw 0x67 sed_patt_ l_ q1 [7:0] sed_pattern _f all _ q1 [7:0] 0x00 rw 0x68 sed_patt_ h _ q1 [7:0] sed_pattern _f all _ q1 [15:8] 0x00 rw 0x6a parity_ctrl [7:0] p arity_ enable p arity _e ven p arity _err c lear reserved p ar e rrf al p ar e r r is 0x00 rw 0x6b parity_err_ rising [7:0] p arity r ising e dge e rror c ount 0x00 r 0x6c parity_err_ falling [7:0] p arity f alling e dge e rror c ount 0x00 r 0x7f version [7:0] version 0x0 b r rev. a | page 51 of 72 ad9142a data sheet register description s defined reserved bits are those whose reset values are not 0x00. access indicates the read and/or write nature of the registe r. spi configure regist er address: 0x00, reset: 0x00, name: common table 26 . bit descriptions for common bits bit name settings description reset access 6 spi_lsb_first serial port communication, msb - first or lsb - first selection. 0 rw 0 msb first. 1 lsb first. 5 device_reset the device resets when 1 is written to this bit. device_reset is a self clear bit. after the reset, the bit returns to 0 automatically. the readback is always 0. 0 rw power - down control registe r address: 0x01, reset: 0xc0, name: pd_control table 27 . bit descriptions for pd_control bits bit name settings description reset access 7 pd_ i dac the idac is powered down when pd_idac is set to 1. this bit powers down only the analog portion of the idac. the idac digital data path is not affected. 1 rw 6 pd_qdac the qdac is powered down when pd_qdac is set to 1. this bit powers down only the analog portion of the qdac. the qdac digital datapath is not affected. 1 rw 5 pd_datarcv the data interface circuitry is powered down when pd_datarcv is set to 1. this bit powers down the data interface and the w rite side of the fifo. 0 rw 2 pd_device the band gap circuitry is powered down when set to 1. this bit powers down the entire chip. 0 rw 1 pd_dacclk the dac clock powers down when pd_device is set to 1. this bit power s down the dac clocking path and, thus, the majority of the digital functions. 0 rw 0 pd_frame the frame receiver powers down when pd_frame is set to 1. the frame signal is internally pulled low. set to 1 when the frame is not used. 0 rw interrupt enable0 register address: 0x03, reset: 0x00, name: interrupt_enable0 table 28 . bit descriptions for interrupt_enable0 bits bit name settings description reset access 6 enable_sync_lost enable interrupt for sync lost. 0 rw 5 enable_sync_locked enable interrupt for sync lock. 0 rw 4 enable_sync_done enable interrupt for sync done. 0 rw 3 enable_pll_lost enable interrupt for pll lost. 0 rw 2 enable_pll_locked enable interrupt for pll locked. 0 rw 1 enable_over_threshold enable interrupt for overthreshold. 0 rw 0 enable_dacout_muted enable interrupt for dacout muted. 0 rw rev. a | page 52 of 72 data sheet ad9142a interrupt enable1 re gister address: 0x04, reset: 0x00, name: interrupt_enable1 table 29. bit descriptions for interrupt_enable1 bits bit name settings description reset access 7 enable_parity_fail enable interrupt for p arity failure . 0 rw 6 enable_sed_fail enable interrupt for sed failure . 0 rw 5 enable_dll_warning enable interrupt for dll warning. 0 rw 4 enable_dll_locked enable interrupt for dll locked. 0 rw 2 enable_fifo_underflow enable interrupt for fifo underflow. 0 rw 1 enable_fifo_overflow enable interrupt for fifo overflow. 0 rw 0 enable_fifo_warning enable interrupt for fifo warning. 0 rw interrupt flag0 regi ster address: 0x05, reset: 0x00, name: interrupt_flag0 table 30 . bit descriptions for interrupt_flag0 bits bit name settings description reset access 6 sync_lost sync_lost is set to 1 when sync is lost. 0 r 5 sync_locked sync_locked is set to 1 when sync is locked. 0 r 4 sync_done sync_done is set to 1 when sync is done. 0 r 3 pll_lost pll_lo st is set to 1 when pll loses lock. 0 r 2 pll_locked pll_locked is set to 1 when pll is locked. 0 r 1 over_threshold over_threshold is set to 1 when input power is overthreshold. 0 r 0 dacout_muted dacout_muted is set to 1 when the dac output is muted (midscale dc). 0 r interrupt flag1 regi ster address: 0x06, reset: 0x00, name: interrupt_flag1 table 31 . bit descriptions for interrupt_flag1 bits bit name settings description reset access 7 parity_fail parity_fail is set to 1 when the parity check fails . 0 r 6 sed_fail sed_fail is set to 1 when the sed comparison fails . 0 r 5 dll_warning dll_warning is set to 1 when the dll raises a warning. 0 r 4 dll_locked dll_locked is set to 1 when the dll is locked. 0 r 2 fifo_underflow fifo_underflow is set to 1 when the fifo read pointer catches the fifo write pointer. 0 r 1 fifo_overflow fifo_overflow is set to 1 when the when the fifo read pointer catches the fifo read pointer. 0 r 0 fifo_warning fifo_warning is set to 1 when the fifo is one slot from empty (1) or full (6). 0 r rev. a | page 53 of 72 ad9142a data sheet interrupt select0 re gister address: 0x07, reset: 0x00, name: irq_sel0 table 32 . bit descriptions for irq_sel0 bits bit name settings description reset access 6 sel_sync_lost 0 selects the irq1 pin. 0 rw 1 selects the irq2 pin. 5 sel_sync_locked 0 selects the irq1 pin. 0 rw 1 selects the irq2 pin. 4 sel_sync_done 0 selects the irq1 pin. 0 rw 1 selects the irq2 pin. 3 sel_pll_lost 0 selects the irq1 pin. 0 rw 1 selects the irq2 pin. 2 sel_pll_locked 0 selects the irq1 pin. 0 rw 1 selects the irq2 pin. 1 sel_over_threshold 0 selects the irq1 pin. 0 rw 1 selects the irq2 pin. 0 sel_dacout_muted 0 selects the irq1 pin. 0 rw interrupt select1 re gister address: 0x08, reset: 0x00, name: irq_sel1 table 33 . bit descriptions for irq_sel1 bits bit name settings description reset access 7 sel_parity_fail 1 selects the irq2 pin. 0 rw 0 selects the irq1 pin. 6 sel_sed_fail 1 selects the irq2 pin. 0 rw 0 selects the irq1 pin. 5 sel_dll_warning 0 selects the irq1 pin. 0 rw 4 sel_dll_locked 1 selects the irq2 pin. 0 rw 0 selects the irq1 pin. 2 sel_fifo_underflow 1 selects the irq2 pin. 0 rw 0 selects the irq1 pin. 1 sel_fifo_overflow 1 selects the irq2 pin. 0 rw 0 selects the irq1 pin. 0 sel_fifo_warning 1 selects the irq2 pin. 0 rw 0 selects the irq1 pin. f rame m ode register address: 0x09 , reset: 0x 00 , n ame: frame_mode table 34. bit descriptions for frame_mode bits bit name description reset access 5 parusage must set to 1 when parity is used 0 rw 4 frmusage must set to 1 when frame is used. 0 rw [1:0] frame_pin_usage 0 = n o e ffect . 1 = p arity . 2 = f rame . 3 = reserved . 0x0 rw rev. a | page 54 of 72 data sheet ad9142a d ata c ontrol 0 register address: 0x0a , reset: 0x 40 , n ame: data_cntr_0 table 35 . bit descriptions for data_cntr_0 bits bit name description reset access 7 dll_enable 1 = e nable dll . 0 rw 0 = disable dll. 6 duty_correction_enable 1 = e nable d uty c ycle c orrection . 1 rw 0 = disable duty cycle correction . [3:0] dll_phase_offset locked p hase = 90 + n 11.25 , where n is the 4 bit signed magnitude number. valid phase setting ranges from ? 6 to + 6, 13 phases in total. 0x0 rw d ata c ontrol 1 register address: 0x0b , reset: 0x 39 , n ame: data_cntr_1 table 36 . bit descriptions for data_cntr_1 bits bit name description reset access 7 clear_warn 1= clears data receiver warning bit s (register 0x0e[6:4]) . 0 rw [6:0] reserved must write the default value for optimal performance . 0x39 rw d ata c ontrol 2 register address: 0x0c , reset: 0x 64 , n ame: data_cntr_2 table 37 . bit descriptions for data_cntr_2 bits bit name description reset access [ 7:0] reserved must write the default value for optimal performance . 0 x64 rw d ata c ontrol 3 register address: 0x0d , reset: 0x 06 , n ame: data_cntr_3 table 38 . bit descriptions for data_cntr_3 bits bit name description reset access 7 lowdcien set to 0 when dll is enabled and dci rate is 350 mhz. set to 1 when dll is enabled and dci rate is < 350 mhz. 0 rw 4 dccouplelowen set to 0 when dll is enabled and delay line is disabled. set to 1 when dll is disabled and delay line is enabled. it is recommended that dll mode be used for a dci rate faster than 250 mhz and the delay line mode be used for dci rate slower than 250 mhz. 0 rw [3:0] reserved must write the default value for opt imal performance . 0x 6 rw data status 0 regist er address: 0x0e, reset: 0x00, name: data_stat_0 table 39 . bit descriptions for data_stat_0 bits bit name description reset access 7 dll_lock 1 = dll lock . 0 r 6 dll_warn 1 = dll near beginning/end of delay line . 0 r 5 dll_start_warning 1 = dll at beginning of delay line . 0 r 4 dll_end_warning 1 = dll at end of delay line . 0 r 3 reserved reserved. 0 r 2 dci_on 1 = user has provided a clock >100 mhz . 0 r 1 reserved reserved . 0 r 0 dll_running 1 = closed loop dll attempting to lock . 0 = delay fixed at middle of delay line . 0 r rev. a | page 55 of 72 ad9142a data sheet dac clock receiver c ontrol register address: 0x1 0, reset: 0xff, n ame: dacclk_receiver_ctrl table 40. bit descriptions for dacclk_receiver_ctrl bits bit name settings description reset access 7 dacclk_dutycycle_correction enables duty cycle correction at the dacclk input. for best performance, the default and recommended status is turned on. 1 rw 6 reserved must write the default value for optimal performance 1 rw 5 dacclk_crosspoint_ctrl_enable enables crosspoint control at the dacclk input. for best performance, the default and recommended status is turned on. 1 rw [4:0] dacclk_crosspoint_level a twos complement value. for best performance, it is recommended to set dacclk_crosspoint_level to the default value. 0x1f rw 01111 highest crosspoint. 11111 lowest crosspoint. ref clock receiver c ontrol register address: 0x11, r eset: 0x 5 f, na me: refclk_receiver_ctrl table 41 . bit descriptions for refclk_receiver_ctrl bits bit name settings description reset access 7 dutycycle_correction enables duty cycle correction at the refx/syncx input. for best performance, the default and recommended status is turned off. 0 rw 6 reserved must write the default value for optimal performance 1 rw 5 refclk_crosspoint_ctrl_enable enables crosspoint control at the refx/syncx input. for best performance, the default and recommended status is turned off. 0 rw [4:0] refclk_crosspoint_level a twos complement value. for best performance, it is recommended to set refclk_crosspoint_level to the default value. 0x1f rw 01111 highest crosspoint. 11111 lowest crosspoint. p ll control 0 register address: 0x12, reset: 0x00, name: pll_ctrl0 table 42 . bit descriptions for pll_ctrl0 bits bit name settings description reset access 7 pll_enable enables pll clock multiplier. 0 rw 6 auto_manual_sel pll band selection mode. 0 rw 0 automatic mode. 1 manual mode. [5:0] pll_manual_band pll band setting in manual mode. 64 bands in total, covering a 1 ghz to 2.1 ghz vco range. 0x00 rw 000000 lowest band (1 ghz). 111111 highest band (2.1 ghz). rev. a | page 56 of 72 data sheet ad9142a pll control 2 register address: 0x14, reset: 0xe7, name: pll_ctrl2 table 43 . bit descriptions for pll_ctrl2 bits bit name settings description reset access [7:5] pll_loop_bw selects the pll filter bandwidth. the default and recommended setting is 111 for optimal pll performance. 0x7 rw 0x00 lowest setting. 0x1f highest setting. [4:0] pll_cp_current sets nominal pll charge pump current. the default and recommended setting is 00111 for optimal pll performance. 0x07 rw 0x00 lowest setting. 0x1f highest setting. pll control 3 register address: 0x15, reset: 0xc9, name: pll_ctrl3 table 44 . bit descriptions for pll_ctrl3 bits bit name settings description reset access [7:6] diglogic_divider refclk to pll digital clock divide ratio. the pll digital clock drives the internal pll logics. the divide ratio must be set to ensure that the pll digital clock is less than 75 mhz. 0x3 rw 00 f refclk /f dig = 2. 01 f refclk /f dig = 4. 10 f refclk /f dig = 8. 11 f refclk /f dig = 16. 4 crosspoint_ctrl_en enable loop divider crosspoint control. the default and recommended setting is set to 0 for optimal pll performance. 0 rw [3:2] vco_divider pll vco divider. this divider determines the ratio of the vco frequency to the dacclk frequency. 0x2 rw 00 f vco /f dacclk = 1. 01 f vco /f dacclk = 2. 10 f vco /f dacclk = 4. 11 f v co /f dacclk = 4. [1:0] loop_divider pll divider. this divider determines the ratio of the dacclk frequency to the refclk frequency. 0x1 rw 00 f dacclk /f refclk = 2. 01 f dacclk /f refclk = 4. 10 f dacclk /f refclk = 8. 11 f dacclk /f refclk = 16. pll status 0 register address: 0x16, reset: 0x00, name: pll_status0 table 45 . bit descriptions for pll_status0 bits bit name settings description reset access 7 pll_lock pll clock multiplier output is stable. 0 r [3:0] vco_ctrl_voltage_readback vco control voltage readback . a binary value. 0x0 r 1111 the highest vco control voltage. 0111 the midvalue when a proper vco band is selected. when the pll is locked, selecting a higher vco band decreases this value and selecting a lower vco band increases this value. 0000 the lowest vco control voltage. rev. a | page 57 of 72 ad9142a data sheet pll status 1 register address: 0x17, reset: 0x00, name: pll_status1 table 46 . bit descriptions for pll_status1 bits bit name settings description reset access [5:0] pll_band_readback indicates the vco band currently selected. 0x00 r i dac fs adjust lsb re gister address: 0x18, reset: 0xf9, name: i dac_fs_adj0 table 47 . bit descriptions for i dac_fs_adj0 bits bit name settings description reset access [7:0] i dac_fullscale_adjust_lsb idac full - scale adjust, these bits, along with bits[1:0] in register 0x19, s et the full - scale current of the i dac. the full - scale current can be adjusted from 8.64 ma to 31.68 ma. the default value (0x1f9) sets the full - scale curr ent to 20 ma. 0xf9 rw i dac fs adjust msb re gister address: 0x19, reset: 0xe1, name: i dac_fs_adj1 table 48 . bit descriptions for i dac_fs_adj1 bits bit name settings description reset access [7:5] reserved se t to default value for optimal performance. 0x7 rw [1:0] i dac_fullscale_adjust_msb i dac full - scale adjust, these bits, along with bits[7:0] in register 0x18, the full - scale current of the i dac. the full - scale current can be adjusted from 8.64 ma to 31.68 ma. the default value (0x1f9) sets the full - scale current to 20 ma. 0x1 rw qdac fs adjust lsb r egister address: 0x1a, reset: 0xf9, name: qdac_fs_adj0 table 49 . bit descriptions for qdac_fs_adj0 bits bit name settings description reset access [7:0] qdac_fullscale_adjust_lsb qdac full - scale adjust , these bits, along with bits [ 1 :0] in register 0x1b, set the full - scale current of the qdac . the fu ll - scale current can be adjusted from 8.64 ma to 31.68 ma. the default value (0x1f9) sets the full - scale current to 20 ma. 0xf9 rw qdac fs adjust msb r egister address: 0x1b, reset: 0x01, name: qdac_fs_adj1 table 50 . bit descriptions for qdac_fs_adj1 bits bit name settings description reset access [1:0] qdac_fullscale_adjust_msb qdac full - scale adjust , these bits, along with bits [ 7 :0] in register 0x1a, set the full - scale current of the qdac . the fu ll - scale current can be adjusted from 8.64 ma to 31.68 ma. the default value (0x1f9) sets the full - scale current to 20 ma. 0x1 rw rev. a | page 58 of 72 data sheet ad9142a die temperature sens or control register address: 0x1c, reset: 0x02, name: die_temp_sensor_ctrl table 51 . bit descriptions for die_temp_sensor_ctrl bits bit name settings description reset access [6:4] fs_current temperature sensor adc full - scale current. using the default setting is recommended. 0x0 rw 000 50 a. 001 62.5 a. 110 125 a. 111 137.5 a. [3:1] ref_current temperature sensor adc reference current. using the default setting is recommended. 0x1 rw 000 12.5 a. 001 19 a. 110 50 a. 111 56.5 a. 0 die_temp_sensor_en enable the on - chip temperature sensor. 0x0 rw die temperature lsb register address: 0x1d, reset: 0x00, name: die_temp_lsb table 52 . bit descriptions for die_temp_lsb bits bit name settings description reset access [7:0] die_temp_lsb die temperature, these bits, along with bits[ 7 :0] in register 0x1e, indicate the approximate die temperature . for more information, see the temperature s ensor section. 0x00 r die temperature msb register address: 0x1e, reset: 0x00, name: die_temp_msb table 53 . bit descriptions for die_temp_msb bits bit name settings description reset access [7:0] die_temp_msb die temperature, these bits, along with bits[ 7 :0] in register 0x1d, indicate the approximate die temperature . for more information, see the temperature s ensor section. 0x00 r chip id register address: 0x1f, reset: 0x 0a, name: chip_id table 54 . bit descriptions for chip_id bits bit name settings description reset access [7:0] chip_id the ad9142a chip id is 0x0a. 0x0a r interrupt c onfiguation register address: 0x20, reset: 0x00, name: interrupt _ config table 55 . bit descriptions for interrupt_config bits bit name settings description reset access [7:0] interrupt _ c onfiguration 0x00 test m ode . 0x00 rw 0x01 recommended mode (described in the interrupt request operation section) . rev. a | page 59 of 72 ad9142a data sheet sync control register address: 0x21, reset: 0x00, name: sync_ctrl table 56 . bit descriptions for sync_ctrl bits bit name settings description reset access 1 sync_clk_edge_sel selects the samp ling edge of the dacclk on the sync clock . 0 rw 0 sync clk is sampled by the falling edges of dacclk. 1 sync clk is sampled by the rising edges of dacclk. 0 sync_enable enables multichip synchronization. 0 rw frame reset control register address: 0x22, reset: 0x12, name: frame_rst_ctrl table 57 . bit descriptions for frame_rst_ctrl bits bit name settings description reset access 3 arm_frame this bit is used to retrigger a frame reset in one shot mode (when b it 2 is set to 0). setting this bit to 1 requests the device to respond to the next valid frame pulse. 0 rw 2 en_con_frame_reset f rame reset mode selection. 0 rw 0 r esponds to the first valid frame pulse and resets the fifo one time only. this is the default and recommended mode. 1 responds to every valid frame pulse and resets the fifo continuously. [1:0] frame_reset_mode the se bits determ ine what is to be reset when the device receives a valid frame signal. 0x2 rw 00 fifo only. 01 nco only. 10 fifo and nco . 11 none. fifo level configura tion register address: 0x23, reset: 0x40, name: fifo_level_config table 58. bit descriptions for fifo_level_config bits bit name settings description reset access [6:4] integer_fifo_level_request these bits s et the integer fifo level. this is the difference between the read pointer and the write pointer values in the unit of input data rate (f data ). the default and recommended fifo level is integer level = 4 and fractional level = 0. see the fifo operation section for details. 0x4 rw 000 0. 001 1. 111 7. [2:0] fractional_fifo_level_request set the fractional fifo level. this is the difference between the read pointer and the write pointer values in the unit of dacclk rate ( f dac ). the maximum allowed setting value = interpolation rate ? 1. see the fifo operation section for details. 0x0 rw 000 0. 001 1. rev. a | page 60 of 72 data sheet ad9142a fifo level readback register address: 0x24, reset: 0x00, name: fifo_level_readback table 59 . bit descriptions for fifo_level_readback bits bit name settings description reset access [6:4] integer_fifo_level_readback the integer fifo level read back. the difference between the overall fifo level request and readback should be within t wo dacclk cycles. see the fifo operation section for details. 0x0 r [2:0] fractional_fifo_level_readback the fractional fifo level read back. this value should be used in combination with the readback i n bit s [ 6:4]. 0x0 r fifo control register address: 0x25, reset: 0x00, name: fifo_ctrl table 60 . bit descriptions for fifo_ctrl bits bit name settings description reset access 1 fifo_spi_reset_ack acknowledge a serial port initialized fifo reset. 0x0 r 0 fifo_spi_reset_request initialize a fifo reset via the serial port. 0x0 rw data format select r egister address: 0x26, reset: 0x00, name: data_format_sel table 61 . bit descriptions for data_format_sel bits bit name settings description reset access 7 data_format select binary or twos complement data format. 0x0 rw 0 input data in twos complement format. 1 input data in binary format. 6 data_pairing indicate i/q data pairing on data input. 0x0 rw 0 i samples are paired with the next q samples. 1 i samples are paired with the prior q samples. 5 data_bus_invert swap the bit order of the data input port. msbs become the lsbs: d[15:0] changes to d[0:15]. 0x0 rw 0 the order of the data bits corresponds to the pin descriptions in table 9 . 1 the order of the data bits is inverted. 0 data_bus_width data interface mode. see the lvds input data ports section for information about the operation of the different interface modes. 0x0 rw 0 word interface mode; 16 - bit interface bus width. 1 byte interface mode; 8 - bit interface bus width. datapath control reg ister address: 0x27, reset: 0x00, name: datapath_ctrl table 62 . bit descriptions for datapath_ctrl bits bit name settings description reset access 7 invsinc_enable enable the inverse sinc filter. 0x0 rw 6 nco_enable enable the nco. 0x0 rw 5 iq_gain_adj_dcoffset_enable enable digital iq gain adjustment and dc offset. 0x0 rw 4 iq_phase_adj_enable enable digital iq phase adjustment. 0x0 rw 2 fs4_modulation_enable enable f s /4 modulation function. 0x0 rw 1 nco_sideband_sel s elect s the single - side nco modulation image. 0x0 rw 0 the nco outputs the high - side image. 1 the nco outputs the low - side image. 0 send_idata_to_qdac send the idata to the qdac. when enabled, i data is sent to both the idac and the qdac. the q data path still runs, and the q data is ignored. 0x0 rw rev. a | page 61 of 72 ad9142a data sheet interpolation contro l register address: 0x28, reset: 0x00, name: interpolation_ctrl table 63 . bit descriptions for interpolation_ctrl bits bit name settings description reset access [1:0] interpolation_mode interpolation rate and mode selection. 0x0 rw 00 2 mode; use hb1 filter. 10 4 mode; use hb1 and hb2 filters. 11 8 mode; use all three filters (hb1, hb2 , and hb3) . over threshold c ontrol 0 register address: 0x29, reset: 0x00, name: over_threshold_ctrl0 table 64. bit descriptions for over_threshold_ctrl0 bits bit name settings description reset access [7:0] threshold_level_request_lsb these bits, along with bits[4:0] in register 0x2a, set the minimum average input power (i 2 + q 2 ) to trigger the input power protection function. 0x0 rw over threshold c ontrol 1 register address: 0x2a, reset: 0x00, name: over_threshold_ctrl1 table 65 . bit descriptions for over_threshold_ctrl1 bits bit name settings description reset access [4:0] threshold_level_request_msb these bits, along with bits[7:0] in register 0x29, set the m inimum average input power (i 2 + q 2 ) to trigger the input power protection function. 0x00 rw over threshold c ontrol 2 register address: 0x2b, reset: 0x00, name: over_threshold_ctrl2 table 66 . bit descriptions for over_threshold_ctrl2 bits bit name settings description reset access 7 enable_protection enable input power protection. 0x0 rw 6 iq_data_swap swap i and q data in average power calculation. 0x0 rw [3:0] sample_window_length number of data input samples for power averaging. 0x0 rw 0000 512 iq data sample pairs. 0001 1024 iq data sample pairs. 1010 2 19 iq data sample pairs. 1011 to 1111 invalid. input power readback lsb register address: 0x2c, reset: 0x00, name: input_power_readback_lsb table 67 . bit descriptions for input_power_readback_lsb bits bit name settings description reset access [7:0] i nput_power_readback_lsb these bits, along with bits[4:0] in register 0x2d, set the input signal average power readback. 0x0 r rev. a | page 62 of 72 data sheet ad9142a input power readback msb register address: 0x2d, reset: 0x00, name: input_power_readback_msb table 68. bit descriptions for input_power_readback_msb bits bit name settings description reset access [4:0] input_power_readback_msb these bits, along with bits[7:0] in register 0x2c, set the i nput signal average power readback. 0x00 r nco control register address: 0x30, reset: 0x00, name: nco_ctrl table 69 . bit descriptions for nco_ctrl bits bit name settings description reset access 6 nco_frame_update_ack frequency tuning word update request from frame. 0x0 r 5 spi_nco_phase_rst_ack nco phase spi reset acknowledge. 0x0 r 4 spi_nco_phase_rst_req nco phase spi reset request. 0x0 rw 1 nco_spi_update_ack frequency tuning word update acknowledge. 0x0 r 0 nco_spi_update_req frequency tuning word update request from spi. 0x0 rw nco frequency t uning w ord 0 register address: 0x31, reset: 0x00, name: nco_freq_tuning_word0 table 70 . bit descriptions for nco_freq_tuning_word0 bits bit name settings description reset access [7:0] nco_ftw0 bits [ 7:0] together with the bits in register 0x32, register 0x33, and register 0x34 form the 32 - bit frequency tuning word that determines the frequency of the complex carrier generated by the on - chip nco. the frequency is not updated when the ftw registers are written. the values are only updated when a serial port update or frame update is initialized in register 0x30. it is in twos complement format. 0x00 rw nco frequency tuning word 1 register address: 0x32, reset: 0x00, name: nco_freq_tuning_word1 table 71 . bit descriptions for nco_freq_tuning_word1 bits bit name settings description reset access [7:0] nco_ftw1 bits [ 7 :0] together with the bits in register 0x31, register 0x33, and register 0x34 form the 32 - bit frequency tuning word that determines the frequency of the complex carrier generated by the on - chip nco. the frequency is not updated when the ftw registers are written. the values are only updated when a serial port update or frame update is in itialized in register 0x30. it is in twos complement format. 0x00 rw nco frequency tuning word 2 register address: 0x33, reset: 0x00, name: nco_freq_tuning_word2 table 72 . bit descriptions for nco_freq_tuning_word2 bits bit name settings description reset access [7:0] nco_ftw2 bits [ 7:0] together with the bits in register 0x31, register 0x32, and register 0x34 form the 32 - bit frequency tuning word that determines the frequency of the complex carrier generated by the on - chip nco. the frequency is not updated when the ftw registers are written. the values are only updated when a serial port update or frame update is initialized in register 0x30. it is in twos complement format. 0x00 rw rev. a | page 63 of 72 ad9142a data sheet nco frequency tuning word 3 register address: 0x34, reset: 0x10, name: nco_freq_tuning_word3 table 73 . bit descriptions for nco_freq_tuning_word3 bits bit name settings description reset access [7:0] nco_ftw3 bits [ 7:0] together with the bits in register 0x31 through register 0x33 form the 32 - bit frequency tuning word that determines the frequency of the complex carrier generated by the on - chip nco. the frequency is not updated when the ftw registers are written. the val ues are only updated when a serial port update or frame update is initialized in register 0x30. it is in twos complement format. 0x10 rw nco p hase o ffset 0 register address: 0x35, reset: 0x00, name: nco_phase_offset0 table 74 . bit d escriptions for nco_phase_offset0 bits bit name settings description reset access [7:0] nco_phase_offset_lsb this register , together with register 0x36, sets the initial phase of the complex carrier signal upon reset. the phase offset spans from 0 to 360 . each bit represent s an offset of 0.0055. this value is in twos complement format. 0x00 rw nco p hase o ffset 1 register address: 0x36, reset: 0x00, name: nco_phase_offset1 table 75 . bit descriptions for nco_phase_offset1 bits bit name settings description reset access [7:0] nco_phase_offset_msb this register , together with register 0x35, sets the initial phase of the complex carrier signal upon reset. the phase offset spans from 0 to 360 . each bit represent s an offset of 0.0055 . this value is in twos complement format. 0x00 rw iq phase adjust 0 register address: 0x37, reset: 0x00, name: iq_phase_adj0 table 76 . bit descriptions for iq_phase_adj0 bits bit name settings description reset access [7:0] iq_phase_adj_lsb q phase ad j ust, bits [ 7:0] along with bits[4:0] in register 0x38, is used to insert a phase offset between the i and q datapaths. it provides an adjustment range of 14 with a step of 0.0035 . this value is in twos complement . see t he quadrature phase adjustment section for more information. 0x00 rw iq phase adjust 1 register address : 0x38, reset: 0x00 , name: iq_pha se_adj1 table 77 . bit descriptions for iq_phase_adj1 bits bit name settings description reset access [4:0] iq_phase_adj_msb iq phase ad j ust, bits [ 4:0] along with bits[7:0] in register 0x37 , is used to insert a phase offset between the i and q datapaths. it provides an adjustment range of 14 with a step of 0.0035 . this value is in twos complement . see the quadrature phase adjustment section for more information. 0x0 rw rev. a | page 64 of 72 data sheet ad9142a p ower d own d ata i nput 0 r egister address: 0x39, reset: 0x00, name: lvds_in_pwr_down_0 table 78 . bit descriptions for lvds_in_pwr_down_0 bits bit name settings description reset access [3:0] pwr_down_data_input_bits powers down data input d[3:0]. each bit controls one data input bit. these bits can be powered down individually. 0x0 rw i dac dc o ffset 0 register address: 0x3b , reset: 0x00, name: idac_ dc_ offset0 table 79 . bit descriptions for idac _dc_ offset0 bits bit name settings description reset access [7:0] i dac_dc_offset_lsb dac dc o ffset , bits [ 7:0] along with bits[7:0] in register 0x3c, is a dc val ue that is added directly to the sample values written to the dac. 0x00 rw i dac dc offset 1 register address: 0x3c, reset: 0x00, name: idac _ dc_ offset 1 table 80 . bit descriptions for idac _ dc_ offset 1 bits bit name settings description reset access [7:0] i dac_dc_offset_msb dac dc o ffset , bits [ 7:0] along with bits[7:0] in register 0x3b , is a dc val ue that is added directly to the sample values written to the dac. 0x00 rw q dac dc offset 0 register address: 0x3d, reset: 0x00, name: qdac _ dc_ offset0 table 81 . bit descriptions for qdac _ dc_ offset0 bits bit name settings description reset access [7:0] qdac_dc_offset_lsb qdac dc o ffset , bits [ 7:0] along with bits[7:0] in register 0x3e, is a dc value that is added directly to the sample values written to the qdac. 0x00 rw qdac dc offset 1 register address: 0x3e, reset: 0x00, name: qdac _ dc_ offset1 table 82 . bit descriptions for qdac _ dc_ offset1 bits bit name settings description reset access [7:0] qdac_dc_offset_msb qdac dc o ffset , bits [ 7:0] along with bits[7:0] in register 0x3d , is a dc value that is added directly to the sample values written to the qdac. 0x00 rw i dac g ain a djust register address: 0x3f, reset: 0x20, name: i dac_gain_adj table 83 . bit descriptions for i dac_gain_adj bits bit name settings description reset access [5:0] i dacgainadj this register is the 6 - bit digital gain adjust on the i channel. the bit weighting is msb = 2 0 , lsb = 2 5 , which yields a multiplier range of 0 to 2 or to 6 db. the default gain setting is 0x20, which maps to unity gain (0 db). 0x20 rw rev. a | page 65 of 72 ad9142a data sheet qdac g ain a djust register address: 0x40, reset: 0x20, name: qdac_gain_adj table 84 . bit descriptions for qdac_gain_adj bits bit name settings description reset access [5:0] qdac_gain_adj this register is the 6 - bit digital gain adjust on the q channel. the bit weighting is msb = 2 0 , lsb = 2 ? 5 , which yields a multiplier range of 0 to 2 or ? to 6 db. the default gain setting is 0x20, which maps to unity gain (0 db). 0x20 rw gain step control 0 register address: 0x41, reset: 0x01, name: gain_step_ctrl0 table 85. bit descriptions for gain_step_ctrl0 bits bit name settings description reset access [5:0] rampupstep this register sets the step size of the increasing gain. the digital gain increases by the configured amount in every four dac cycles until the gain reaches the setting in i dacgainadj (register 0x3f). the bit weighting is msb = 2 1 , lsb = 2 4 . note that t he value in this register must not be greater than the values in the i dacgainadj. 0x01 rw gain step control 1 register address: 0x42, reset: 0x 4 1, name: gain_step_ctrl1 table 86 . bit descriptions for gain_step_ctrl1 bits bit name settings description reset access 7 dac_output_ off this bit allows for turning the dac output on and off manually. the digital iq gain function (register 0x27, bit 5) must be turned on for this bit to function. 0x0 rw 6 dac_output_ status t his bit indicates the dac output on/off status. when the dac output is turned off, this bit i s 1. upon power - up, this bit is 1. the digital iq gain function (register 0x27, bit 5) must be turned on for this bit to track the on/off status 0x 1 r [5:0] ramp_ down_step this register sets the step size of the decreasing gain. the digital gain decreases by the configured amount in every four dac cycle s until the gain reaches zero. the bit weighting is msb = 2 1 , lsb = 2 ? 4 . note that the value in this register must not be greater than the values in the i dac_gain_adj (register 0 x3f ). 0x01 rw t x enable control regis ter address: 0x43, reset: 0x07, name: tx_enable_ctrl table 87 . bit descriptions for tx_enable_ctrl bits bit name settings descr iption reset access 2 txenable_gainstep_en dac output gradually turns on/off under the control of the txenabl e signa l from the txen pin according to the settings in register 0x41 and regis ter 0x42. 1 rw 1 txenable_sleep_en when set to 1, the device is put in sleep mode when the txenable si gnal from the txen pin is low. 1 rw 0 txenable_power_down_en when set to 1, the device is put in power down mode when the txenable signal from the txen pin is low. 1 rw rev. a | page 66 of 72 data sheet ad9142a dac output control r egister address: 0x44, reset: 0x8 d , name: dac_output_ctrl table 88 . bit descriptions for dac_output_ctrl bits bit name settings description reset access 7 dac_output_ctrl_en enable s the dac output control. this bit needs to be set to 1 to enable the re maining bits in this register. 0x1 rw 3 fifo_warning_shutdown_en when this bit and bit 7 are both high, if a fifo warning occurs, the dac output shuts down automatically. by default, this function is on. 0x1 rw 2 overthreshold_shutdown_en the dac output is turned off when the input average power is greater than the predefined threshold. 0x1 rw 0 fifo_error_shutdown_en the dac output is turned off when the fifo reports warnings. 0x1 rw dll c ell e nable 0 register address: 0x5e, reset: 0xff, name: enable_dll_delay_cell 0 table 89 . bit descriptions for enable_dll_delay_cell0 bits bit name description reset access [7:0] delay_cell_enable [7:0] set each bit to enable or disable the delay cell. delay cell number corresponds to bit number. 0xff rw 1 = e nable delay cell (default). 0 = d isable delay cell. different recommended values should be used in dll mode and delay line mode. see the data interface section. dll c ell e nable 1 register address: 0x5f, reset: 0x67, name: enable_dll_delay_cell 1 table 90 . bit descriptions f or enable_dll_delay_cell 1 bits bit name description reset access [7:3] reserved must write the default value for optimal performance . 0x0c rw [2:0] delay_cell_e nable [10:8] set each bit to enable or disable the delay cell. delay cell numbers are 10, 9, 8 corresponding to bits bit, bit 2, and bit 0, respectively. 0x7 rw 1 = e nable delay cell (default). 0 = d isable delay cell. sed c ontrol register address: 0x60, reset: 0x00, name: sed_ctrl table 91 . bit descriptions f or sed_ctrl bits bit name description reset access 7 sed_e nable set to 1 to enable the sed c ompare l ogic . 0 rw 6 sed_e rr_c lear when set to 1, clears all sed reported error bit s , bit 2, bit 1, and bit 0. 0 rw 5 aed_e nable when set to 1, enables the aed function ( sed with auto clear after eight passing sets ) . 0 rw 4 sed_depth 0 = sed depth of two words, 1 = sed depth of four words . 0 rw 3 reserved reserved. 0 r 2 aed_pass when aed = 1, it s ignals eight true compare cycles . 0 rw 1 aed_fail when aed = 1, it s ignals a mismatch in comparison . 0 r 0 sed_fail signals that an sed mismatch in comparison occurred ( w ith sed or aed enabled) . 0 r rev. a | page 67 of 72 ad9142a data sheet sed p attern i0 l ow b its register address: 0x61, reset: 0x00, name: sed_patt_l_ i0 table 92 . bit descriptions f or sed_patt_l_ i0 bits bit name description reset access [7:0] sed_pattern_rise_ i0 [7:0] sed i0 rising edge low bits. 0x00 rw sed p attern i 0 h igh b its register address: 0x62, reset: 0x00, name: sed_patt_h_ i 0 table 93 . bit descriptions f or sed_patt_h_ i 0 bits bit name description reset access [7:0] sed_pattern_rise_ i 0[15:8] sed i0 rising edge high bits. 0x00 rw sed pattern q0 low bits register address: 0x63, reset: 0x00, name: sed_patt_l_ q0 table 94 . bit descriptions f or sed_patt_l_ q0 bits bit name description reset access [7:0] sed_pattern_fall_ q0 [7:0] sed q0 falling edge low bits. 0x00 rw sed pattern q0 high bits register address: 0x64, reset: 0x00, name: sed_patt_h_ q0 table 95 . bit descriptions f or sed_patt_h_ q0 bits bit name description reset access [7:0] sed_pattern_fall_ q0 [15:8] sed q0 falling edge high bits. 0x00 rw sed pattern i1 low bits register address: 0x65, reset: 0x00, name: sed_patt_l_ i1 table 96. bit descriptions f or sed_patt_l_ i1 bits bit name description reset access [7:0] sed_pattern_rise_ i1 [7:0] sed i1 rising edge low bits. 0x00 rw sed pattern i1 high bits register address: 0x66, reset: 0x00, name: sed_patt_h_ i1 table 97 . bit descriptions f or sed_patt_h_ i1 bits bit name description reset access [2:0] sed_pattern_rise_ i1 [15:8] sed i1 rising edge high bits. 0x00 rw sed pattern q1 low bits register address: 0x67, reset: 0x00, name: sed_patt_l_ q1 table 98 . bit descriptions f or sed_patt_l_q1 bits bit name description reset access [7:0] sed_pattern_fall_ q1 [7:0] sed q1 falling edge low bits. 0x00 rw rev. a | page 68 of 72 data sheet ad9142a rev. a | page 69 of 72 sed pattern q1 high bits register address: 0x68, reset: 0x00, name: sed_patt_h_q1 table 99. bit descriptions for sed_patt_h_q1 bits bit name description reset access [2:0] sed_pattern_fall_q1[15:8] sed q1 falling edge high bits. 0x00 rw parity control register address: 0x6a, reset: 0x00, name: parity_ctrl table 100. bit descriptions for parity_ctrl bits bit name settings description reset access 7 parity_enable 1 enable parity. 0 rw 6 parity_even 0 odd parity. 0 rw 1 even parity. 5 parity_err_clear set to 1 to clear parity error counters. 0 rw [4:2] reserved reserved. 0x0 r 1 parerrfal when 1, signals a falling edge parity error was detected. 0 r 0 parerrrise when 1, signals a rising edge parity error was detected. 0 r parity error rising edge register address: 0x6b, reset: 0x00, name: parity_err_rising table 101. bit descriptions for parity_err_rising bits bit name description reset access [7:0] parity rising edge error count number of rising edge-based errors detected (s0 and s2). clipped to 256. 0x00 r parity error falling edge register address: 0x6c, reset: 0x00, name: parity_err_falling table 102. bit descriptions for parity_err_falling bits bit name description reset access [7:0] parity falling edge error count number of falling edge-based errors detected (s1 and s3). clipped to 256. 0x00 r version register address: 0x7f, reset: 0x0b, name: version table 103. bit descriptions for version bits bit name settings description reset access [7:0] version chip version. 0x0b r ad9142a data sheet rev. a | page 70 of 72 dac latency and system skews figure 62. breakdown of pipeline latencies dac latency variations dacs, like any other devices with internal multiphase clocks, have an inherent pipeline latency variation. figure 62 shows the delineation of pipeline latencies in the ad9142a . the highlighted section, including the fifo and the clock generation circuitry, is where the pipeline latencies vary. upon each power- on, the status of both the fifo and the clock generation state machine is arbitrary. this leads to varying latency in these two blocks. fifo latency variation there are eight data slots in the fifo. the fifo read and write pointers circulate the fifo from slot 0 to slot 7 and back to slot 0. the fifo depth is defined as the number of fifo slots that are required for the read pointer to catch the write pointer. it is also the time a particular piece of data stays in the fifo from the point that it is written into the fifo to the point where it is read out from the fifo. therefore, the latency of the fifo is equivalent to its depth. figure 63 is an example of fifo latency variation. the latency in case 2 is two data cycles longer than that in case 1. if other latencies are the same, the skew between the dac outputs in these two cases is, likewise, two data cycles. therefore, to keep a constant fifo latency, the fifo depth needs to be reset to a pre- defined value. theoretically, any value other than 0 is valid but typically it is set to 4 to maximize the capacity of absorbing the rate fluctuation between the read and write sides. figure 63. example of fifo latency difference figure 64 shows two equivalent cases of fifo latency of four data cycles. although neither the read nor the write pointer match each other in these two cases, the fifo depth is the same in both cases. also, note that the beginning slots of the data stream in the two cases are not the same, but the read and write pointers point to the same piece of data in both cases. this does not affect the alignment accuracy of the dac outputs as long as the data and the dcis are well aligned at multiple devices. figure 64. example of equal fifo latencies fifo dacclk i and q dac hb1 fixed latency hb2 hb3 other digital functionalities dacclk/2 dacclk/4 dacclk/8 dci fifo wrptr fifo rdptr varying latency varying latency fixed latency div 2 div 2 div 2 data interface 11901-064 data 2 data 3 data 4 data 5 fif o case 1: latency = 4 dci cycles fifo w rptr fifo rdptr data 6 data 7 data 1 data 0 data 2 data 3 data 4 data 5 fifo case 2: latency = 6 dci cycles fifo wrptr fifo rdptr data 6 data 7 data 1 data 0 11901-065 data 2 data 3 data 4 data 5 fif o latency = 4 dci cycles fifo w rptr fifo rdptr data 6 data 7 data 1 data 0 data 7 data 0 data 1 data 2 fifo fifo wrptr fifo rdptr data 3 data 4 data 6 data 5 11901-066 data sheet ad9142a rev. a | page 71 of 72 clock generation latency variation the state machine of the clock generation circuitry is another source of latency variations; this type of latency variation results from inherent phase uncertainty of the static frequency dividers. the divided down clock can be high or low at the rising edge of the input clock, unless specifically forced to a known state. this means that whenever there is interpolation (when slower clocks must be internally generated by dividing down the dacclk), there is an inherent latency variation in the dac. figure 65 is an example of this latency variation in 2 interpolation. there are two phase possibilities in the dacclk/2 clock. the dacclk/2 clock is used to read data from the fifo and to drive the interpolation filter. regardless of which clock edge is used to drive the digital circuit, there is a latency of one dac clock cycle between case 1 and case 2 (see figure 65). because the power- on state arbitrarily falls in one of the two cases, the phase uncertainty of the divider appears as a varying skew between two dac outputs. figure 65. latency variation in 2 interpolation from clock generation correcting system skews generally, it is assumed that the input data and the dci among multiple devices are well aligned to each other. depending on the system design, the data and dci being input into each dac can originate from various fpgas or asics. without synchronizing the data sources, the output of one data source can be skewed from that of another. the alignment between multiple data sources can also drift over temperature. figure 66 shows an example of a 2-channel transmitter with two data sources and two dual dacs. a constant but unknown phase offset appears between the outputs of the dac devices, even if the dac does not introduce any latency variations. the multidevice synchronization in the ad9142a can be used to compensate the skew due to misalignment of the data sources by resetting the two sides of the fifo independently through two external reference clocks: the frame and the sync clock. the offset between the two data sources is then absorbed by the fifo and clock generation block in the dac. for more information about using the multidevice synchronization function, refer to the synchronization implementation section. figure 66. dac output skew fr om skewed input data and dci hb1 hb2 hb3 dacclk dacclk/2 (case 1) dacclk/2 (case 2) latency variation = 1 dacclk cycle 11901-067 dac dac dac dac 16-bit data frame dci 16-bit data frame dci 16-bit data frame dci dci 16-bit data frame sync clock 4 2 match sync line for all data gen data skew data gen data gen master ref clock 11901-068 ad9142a data sheet rev. a | page 72 of 72 packaging and ordering information outline dimensions figure 67. 72-lead lead frame chip scale package [lfcsp_vq] 10 mm 10 mm body, very thin quad (cp-72-7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9142abcpz ?40c to +85c 72-lead lfcsp_vq cp-72-7 ad9142abcpzrl ?40c to +85c 72-lead lfcsp_vq cp-72-7 AD9142A-M5372-EBZ evaluation board connected to adl5372 modulator ad9142a-m5375-ebz evaluation board connected to adl5375 modulator 1 z = rohs compliant part. compliant to jedec standards mo-220-vnnd-4 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 0.05 max 0.02 nom 1 18 54 37 19 36 72 55 0.50 0.40 0.30 8.50 ref pin 1 indicator seating plane 12 max 0.60 0.42 0.24 0.60 0.42 0.24 0.30 0.23 0.18 0.50 bsc pin 1 indicator coplanarity 0.08 06-25-2012-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. top view exposed pa d bottom view 10.10 10.00 sq 9.90 9.85 9.75 sq 9.65 0.25 min 6.15 6.00 sq 5.85 ?2013C2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d11901-0-5/14(a) |
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